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HP Introduces Final Processor in PA-RISC Family
The HP Way writes "According to an article on InformationWeek, HP announced the immediate availability of the 800 MHz, 1.0 GHz, and 1.1 GHz dual-core PA-8900 with 64MB on die L2 cache, the last member of the PA-RISC family of microprocessors. Customers with Superdome chassis can install Itanium 2 CPUs alongside PA-8900 processors."
The user-visible instruction set doesn't matter anymore. There's a wide variety of different architectures under the hood of the various x86-compatible implementations, and these will continue to evolve and improve. The real CPU architecture looks nothing at all like the interface presented to the programmer; this is even true for most recent RISC chips.
If non x86-compatible instruction sets provided a significant benefit, then CPUs using them would have been able to hold a substantial and lasting performance lead over the x86-compatible CPUs. But they haven't. When somebody claims that an alternative CPU architecture is beating the top-end x86 chips, it's usually just because they've slapped a massive cache next to the core. It has little if anything to do with the instruction architecture itself. The x86 instruction format is just a standardized compact bytecode that is translated to the latest features by each generation of x86-compatible microprocessor.
If you can make essentially the same progress without breaking compatibility with a huge body of software which has received so much massive investment, what good does it do to break compatibility?