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AMD Athlon 64 FX-57 Review
Duane writes "GDHardware.com has the first review of AMD's upcoming Athlon 64 FX-57 CPU clocked at 2.8GHz. They benchmark it against Intel's current fastest 3.8GHz P4 and the Athlon 64 X2." From the article: "Clocked at 2.8GHz, the FX-57 continues the 'San Diego' core AMD released with the FX-55, but is stepped up a paltry 200MHz faster. What's interesting is that while 200MHz on the Intel side of things doesn't always mean that great of a performance gain, not so with AMD."
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AMD continues to raise the bar in performance - both in dual core with its recent X2 chip and now once again in the single core design with its pending FX-57 launch due on June 27th.
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The FX-57 is armed with a total of 1152KB of cache (128KB L1 and 1024KB L2) which greatly speeds up commonly called data cues and is a great sized buffer between the CPU and system RAM.
[conclusion]
However, at this point in the game we'd have a hard time giving a full recommendation to anyone to spend close to or over $1000 on a chip that isn't dual core
From what I've read, while Intel can keep cranking up the core speed of their chips, all those clock cycles are wasted if it spends most of its time waiting around for memory. The northbridge on Intel motherboards is now their biggest bottleneck. So at least part of the reason AMD can get better throughput at a lower clockrate is that it eliminates the northbridge altogether, puts the memory controller on the CPU, and ties everything else together using their insanely fast "HyperTransport" system bus. Any engineers who know more about it care to comment?
How the fuck did that get moderated up. It makes no fucking sense and is completely inaccurate (and yes, IAACompEng).
Athlons have higher IPC (instructions per clock) than a P4. Why? The length of the pipeline. Athlon 64s have a SINGLE pipeline, with a length of about 15 (aka "a 15 stage pipeline"). A P4-prescott (90nm version) has a 31 stage pipeline. The P4 northwood had a 20 stage pipeline (note that those are for integer instructions, floating point operations have more stages through the FPU). A64s do not have 9 pipelines, nigh the P4 have 6. And neither get anywhere near the ops/clock you claim. They do have parallel execution units however, and maybe thats where you get your numbers from, but even then they're still not right.
So it takes an integer operation 15 or so cycles to be complete in an Athlon, and 30 cycles in a P4. Thus the higher IPC. Other things also influence performance are cache hit ratio, branch prediction. And thats the reason why the prescott didnt fall on its face-more cache as well as better Branch Prediction Unit (BPU). A lot of improvements went into the 90nm prescott to keep IPC close to what the P4-northwood had. There were some articles at Anandtech when it first came out, comparing it to the northwood.
To parent: Go read some Ars Technica articles about how CPUs are organized before you talk out of your ass about stuff you dont know.
The Doormat
If you're not outraged, then you're not paying attention.
Correct, as far as it goes.
/bubble penalties.
However: it's not the pipeline length causing "15 cycles versus 30 cycles" that will actually harm performance. It's pipeline STALLS what kill performance--in a perfect world, for example, a hypothetical 10,000-stage single-pipeline processor running at 1 GHz would retire 1 BILLION instructions per second, albeit with a 10,000 clock initial pipeline fill upon powerup.
Do something that causes the pipeline to need to be flushed and refilled, however, and you just lost 10,0000 clocks.
This is where the P4 has problems relative to the Athlon: keeping it's pipeline filled, and the subsequent pipeline flush
Note that there's lots more to this discussion than I wrote here (can you say branch predictors, trace caches, lookaside buffers, etc.), but ultimately all that stuff has to do with KEEPING THE PIPELINE FILLED, and what happens when you don't.
- The race is not [always] to the swift, nor the battle to the strong. -
You're asking the wrong question. Even if no one buys this chip, the chip is still worthwhile to have on the market.
A few years ago Wendy's found that almost no one was buying their triple cheeseburgers, so they took triples off the menu. When they did this, they found that sales of their double cheeseburgers dropped to almost nothing. The problem, as they discovered later, was that the presence of triple cheeseburgers on the menu helped to legitimize the double cheeseburgers as mainstream items. Without triple cheeseburgers, the double cheeseburgers became the high end item and mainstream buyers went for the singles instead.
Since profit margins on double cheeseburgers are higher, the chain was forced to bring back triple cheeseburgers, even though triples weren't selling at all, because the sales of their double cheeseburgers depended on having triples on the menu.
Point is, although this is a fast food example, the same thing applies to the computer industry. You HAVE to have a high end item available if you are to have any hope of positioning the more profitable midrange items as mainstream.