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Speculation on Real Reasons Behind Apple Switch
/ASCII writes "There is an article over at Ars Technica with some insider information about the reasons behind Apples x86 switch, given that the new IBM processors seem to be a perfect fit for Apple. The article claims that Apple hopes to power its entire line, from Servers to desktops to iPods and other gadgets with Intel CPUs, and that by doing so, they will gain the same kinds of discounts that Dell get."
They claim -Os is to remove bloat, not increase performance :-) Thing is, for kernel type code the resulting code is actually _faster_ than with gcc -O2, since there is a lot less cache pressure.
The Fedora kernel people have benchmarked this quite a bit (and now compile kernels with -Os too), the difference is quite measurable, 5%:ish in some benchmarks.
Compiling with "-Os" (optimize for smaller code size) is not always at odds with speed, as is implied in the article.
While for some trivial benchmark code -O4 may generate faster code, for real-world applications keeping your code in cache is worth more than loop unrolling - so in real-world stuff often -Os is better than -O[2345].
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No. Volume discounts are not illegal. Only offering volume discounts to customers who stay away from your competitors products might be, but that is not the same thing.
If bulk discounts where illegal, Wallmarts would be out of buisness and everyone would have to shop at 7-11.
Try out fish, the friendly interactive shell.
You, sir, seem to be suffering from a serious humor deficiency.
My recommendation: Go read America's finest news source until you begin to laugh again. Then come back here.
____
~ |rip/\/\aster /\/\onkey
I'm not sure what you mean by this. You should read up on the Church-Turing thesis. Basically, it can be proven that a very simple instruction set (I think the minimum is 3 instructions[1]) can run any algorithm. The question then becomes, what instructions should be implemented as a single instruction on the chip, and which ones should be implemented as a combination of instructions. Generally, it turns out, it is a good idea if all of your instructions take the same length of time to execute - this makes interleaving different instructions much easier. It therefore makes sense to have a relatively simple instruction set.
The trend towards CISC ended with things like the VAX. Back when people used to program in assembly, it made sense to have complex instruction sets to make things easier for the programmer. The VAX included things like an evaluate polynomial instruction, for example. Of course, this was quite unwieldy, and so a lot of the instructions were implemented as microcode - you they were automatically translated to a set of simpler instructions.
With the development of high-level languages, it emerged that compiler writers were not using these complex instructions, they were implementing them directly in simpler instruction. It then made more sense to focus on making a small set of instructions run quickly (which, it turns out, is easier and therefore cheaper).
Note that `CISC' chips are not really CISC anymore. They do the same `emulation' that RISC chips do. When you run x86 code on a Pentium each instruction is broken down into simpler instructions and then these are executed on the RISC core. The Pentium 4 (and, I believe, the Pentium M) cache these micro-instructions, so they don't have to do the translation twice.
[1] Zero, Increment, and Conditional Jump, for example - try it, you can do addition simply, multiplication by repeated addition, then build more complex algorithms from there.
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It's been obvious for a while that the "real reason" is that Apple's needs are met better by Intel's roadmap than IBM's, and Apple doesn't have enough marketshare to make it worthwhile to change that.
Yes, the new 970FX chips are an improvement over the current tech. On the other hand, it's not mind-blowing compared to Intel's current line-up, much less what's in the pipeline. I'm supposed to be impressed by an announced 13W @ 1.4GHz and 16W @ 1.6GHz when Intel has been selling 10W @ 1.5GHz for months?
Even the dual-core Yonah core, slated for volume production first quarter of 2006, is quoted as staying within a 25W envelope @ 2.13GHz. Speeds for the low voltage, ultra low voltage, and single core parts aren't released yet, but Intel has made it clear that it's aggressively pursuing lower power designs and that notebooks based on the next generation of chips will "use approximately 33% less power".
ARM is an instruction set, not a processor. The XScale is an ARM processor.
RISC is a type of instruction set, of which the ARM instruction set is one. ARM also refers to the company that created it, to several of the processors they themselves produced (e.g. ARM 2, ARM 3, ARM 600, StrongARM) and to the cores they sell to other people.
So what's this about "any" P4 vs A64 tests that show that P4s are superior in audio & video compression?
Condemnant quod non intellegunt.
The PPC is just a plain better processor. The x86 has done well, and I'm impressed how far it has come from a chip that originally wasn't powerful enough to be a calculator. The PPC was designed recently, and there fore suffers fewer legacy issues. I mean, Pentium 4's still have real mode, for example.
The G5 was a dandy machine, and our customers couldn't get enough of them. The trouble is, neither could Apple!
Apple was leaving a pile of money behind, every single quarter that they had to put up with IBM's supply limitations. I didn't have access to the figures, but I would estimate that sticking with IBM was costing Apple upwards of a billion in revenue per quarter.
One thing that Apple knows they're going to get from Intel, is reliable supply of all the CPUs they can use.
-jcr
The only title of honor that a tyrant can grant is "Enemy of the State."