Intel Plans to Overhaul Chip Architecture

Carl Bialik from the WSJ writes "Intel is planning to announce an entirely new chip architecture later this month at the company's developer forum, the Wall Street Journal reports. The company isn't discussing details yet, but it's expected that Paul Otellini will discuss a 'technology foundation designed from scratch to improve energy efficiency and make it easier to add more than two processors.'"

Comments

What does this mean?

[AKAImBatman]

One thing the article didn't make clear is what exactly Intel means by "A New Chip Architecture". i.e. Do they mean a new architecture as in the Itanic (but low power!), or a new chip architecture as in, "We're ditching the 20 stage pipeline in exchange for a more reasonable 6 stage pipeline, swapping out most of the control circuts for those from our StrongARM line, and rewriting the microcode to execute all of the Pentium instructions on a simple, low power RISC core."

While they could go either way, I hope they've learned from the Itanium and EM64T debacles that they should stick with a compatible microcode. Leave the super-instruction sets to the MIPS and SPARCs of the world.

Re:What does this mean?

[hotchai]

Nope, this is still the same old x86 architecture we all love. What they mean by a "new architecture" is that they are ditching the Pentium-IV micro-architecture and developing a new one based on the Pentium-M micro-architecture (itself loosely based on the Pentium-!!! design). As a result, the new chips promise to deliver higher performance at lower power levels.

Re:What does this mean?

[dbrutus]

I have a hunch that Steve Jobs knows. Apple goes to Intel during the 2006-2007 time frame because of their low power consumption chips out there on their roadmap. Now Intel is launching low power consumption chips. I would be shocked if Apple didn't have access to early chips as a condition for switching architectures.

It's Conroe

[Hack Jandy]

Conroe according to Anandtech...
http://anandtech.com/cpuchipsets/showdoc.aspx?i=24 92

HJ

totally cool

[ackthpt]

no-way-the-old-architecture-is-totally-cool

This is kinda funny in two ways..

• 1. Intel often comes out with new processors which run HOT, pushing the chip to extremes of physics.
• 2. The old architecture is a dinosaur, harkening back to the 8088 and rather inefficient in many respects, where RISC processors were supposed to trump it. Which is still around? It seems you can come up with all the technological advances you like, so long as it is still a pumped up 8088.

'technology foundation designed from scratch to improve energy efficiency and make it easier to add more than two processors.'

Not overheard anywhere: "We are peeking through a knothole in AMD's fence and seeing what they are up to.

Nitpick: "The company isn't discussed details yet"
The proper word is ain't.

Obligatory obvious sighting

[Iriel]

One has to wonder if Apple had any 'insight' to these plans when they signed the deal.

Re:My guess is a new x86

[philipgar]

No... I doubt they'll be using the Pentium M core for this redesign. The new push will be for multithreading. The pipeline may shrink a bit, but long pipelines are nice because they allow for very high clock speeds due to low fanouts. When designing high power software going from 4 threads to 16 is often not too difficult. At least if you use the right paradigms. Combined with low-latency communication (L2 cache speeds) this makes for a very powerful combination.

When designing such a machine its important to consider what the software will look like. Is it better to run 16 threads each with a CPI (cycles per instruction) of 1.2 or run 32 threads with a CPI of 1.6? This will actually push us much further back than the P3.

The cores on these processors are far more likely to resemble the original Pentiums. Simple pipelines, in-order execution, minimal instruction level parallelism. When the current P4 superscalar beasts can rarly pull a CPI of 1, whats the point of allowing 4 instructions to execute simultaneously (at least if the core is only executing one thread).

The new push will be to have 8 very simple cores (albeit with advanced SSE4 units with even wider vector instructions such as 256 or 512 bits) and allow each core to run 2 or 4 threads. This won't be hyperthreading as hyperthreading is a form of SMT (although Intel may reuse the name). It will be a form of fine-grained multithreading that allows context switches on L1 or L2 cache misses, as well as other latent operations. Of course their will also be logic to allow all the threads to run equally.

With these processors we'll be able to run 16-32 threads simultaneously (or almost simultaneously). For applications that can be massively threaded this will result in a huge boost in performance. For the single threaded applications that aren't easily parallelizable .. . many of them don't need more power than what a simple 4GHz core can offer them. Those that require more computation than that will likely be reprogrammed to support multi-threading.

This technology will scale tremendously. These new processors will essentially be supercomputers on a chip. I think this because of a presentation I saw by one of the lead P4 architects who was talking about future processors. This will be the future, and the time is now to rethink any applications you currently have and find someone competent in multithreading.

Phil

Re:article ignores Pentium M?

[nutshell42]

The other slightly embarrassing (for Intel) twist is that the new architecture will be a lot closer to the P6 than to the P7 ("Netburst") core used in the Pentium-4. Essentially, the Pentium-4 was a dead end, and all Intel's x86 plans now involve Pentium-M derived chips.

Yeah, the idea behind Netburst was to streamline everything for clock frequencies as high as possible. This offered marketing advantages (before ppl became used to AMDs xx00+ ratings) and there was a time (shortly before and after the clawhammer) when it seemed like Intel had been right. It seemed that whatever AMD did Intel could just crank up the frequency another 200MHz, there was already speculation about 6GHz and more. But then they ran into the 4GHz barrier (and they weren't the only ones. IBM originally put the Cell at 4GHz+ and now they seem to have troubles at 3.2GHz) and since then Netburst has been dying a slow and painful death =)