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Branched Nanotubes Offer Smaller Transistors
Designadrug writes "Tiny tubes of carbon, crafted into the shape of a Y, could revolutionize the computer industry, suggests new research. The work has shown that Y-shaped carbon nanotubes are easily made and act as remarkably efficient electronic transistors - but the nanotransistors are just a few hundred millionths of a meter in size -roughly 100 times smaller than the components used in today's microprocessors."
This paper suggests that this sort of thing was being done 5 years ago.
From the paper:
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~ |rip/\/\aster /\/\onkey
In the near-term, we have to be able to sort CNTs by chirality and diameter much more accurately and cheaply than we can now - this is because the properties of CNTs change dramatically based on very slight variations in these properties.
/. people who have access to scientific journals and want more in depth information on this subect - you can take a look at these articles:
Once we can do that reasonably well, there are a few approaches that look promising. For
P. G. Collins, et al., Science, 292, 706 (2001)
P. G. Collins, M. C. Hersam, M. Arnold, R. Martel, and Ph. Avouris, Phys. Rev. Lett., 86, 3128 (2001).
J. A. Misewich, et al., Science, 300, 783 (2003)
It's also Carbon, something regularly used for resistors (prior to film resistors.) Seems resistance and heat will be some kind of issue.
As to "how do you solder them," that's just stupid. You don't solder them, any more than you solder 100 million transistors in a Pentium.
Pentium and other chips are etched from an existing sandwich, IIRC, we're talking about growing a "chip" rather than chiseling the everything from a section of a wafer which doesn't look like a Pentium.
A feeling of having made the same mistake before: Deja Foobar
There was an article in Sientific American about making chips much smaller by letting water flow between the imprinting laser lens and the silicon wafer. The water changes the refractive index, so the lens can be better utilized, as I understand it, and apparently it's not particularly difficult either, since existing 193nm lithography can be used, and even surpass the planned 157nm lithography tech. Here's another article with some links.
True confidence comes not from realising you are as good as your peers, but that your peers are as bad as you are.
What you have to remember about heat is that electronics only get hot because they are never perfect conductors nor perfect insulators {though we can make nearer-perfect insulators than we can conductors}. A perfect conductor will never get hot, no matter how much current you put through it, because the voltage drop across it will be nil and power = voltage * current. Nor will a perfect insulator, because this time, the current through it will be nil.
..... hopefully a fuse.
CMOS is based around two transistors, a P-channel FET which goes conductive when the gate is driven low, and an N-channel FET which goes conductive when the gate is driven high. The P-FET is trying to pull the output high and the N-FET is trying to pull it low. Both the gates are joined together, and this is the input. This is a simple NOT gate.
For a NAND gate, where any input 0 will drive the output to a 1, we have several P-FETs in parallel trying to drive the output high, and so many N-FETs in series trying to drive the output low. Each P-FET gate joined to an N-FET gate is one input. When they are all high, all the N-FETs turn on allowing the output to go low; when any one is low, the chain of N-FETs is broken, one or more P-FETs turn on, and the output goes high. For a NOR gate, where any input 1 will drive the output to a 0, we put the Ns in parallel and the Ps in series. You can make AND gates from NAND+NOT, OR gates from NOR+NOT, and any other combination you like. In fact you really don't need both NAND and NOR, because you can make either one out of the other; but it turns out they're equally as easy to make as each other in CMOS {not like many other technologies}.
In an ideal world this would never dissipate any power, since the input cannot be high and low at the same time so only one of the transistors will ever be on. In practice what happens is that the gates act like capacitors which take a finite time to charge and discharge. They do not switch instantaneously from conductive to non-conductive. So one stops conducting while the other is starting to conduct, and for a brief instant while the inputs are changing state both transistors are conducting a little. It's not a dead short circuit of course, otherwise something would give way
Now every time something changes state, you get a little pulse of heat. Which is why fast processors need cooling. Additionally, to make sure that the logic gate output has changed state before the next clock pulse, you need to make the gate capacitances charge up quickly -- which means using a higher voltage than you could get away with at lower speeds. But 2x more volts means 2x more amps means 4x more watts.
Smaller transistors should have less gate capacitance, and so be capable of switching more quickly.
Je fume. Tu fumes. Nous fûmes!
It's also Carbon, something regularly used for resistors (prior to film resistors.) Seems resistance and heat will be some kind of issue.
Actually, carbon nanotubes are as conductive as copper...here's a nice resource .
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~ |rip/\/\aster /\/\onkey
*Sigh*
t orials/Scaling/scaling.html%5BUniversity of Minnesota, Mechanical engineering]
No. Decreasing the size of something -increases- the surface area compared to the volume of the object, increasing it's overall ability to dissipate heat.
http://www.me.umn.edu/education/courses/me5221/Tu
Get your physics straight.
Moore's law applies to transistor counts per square inch, not clock speeds. You're thinking of the "Law of Marketing."
If you don't know where you are going, you will wind up somewhere else.
Do you even know what Moore's law is? Even a highschool student can tell you that it has nothing to do with the MHz speed of the silicon, although theoretically as the widths of the gates shrink you can run the logic faster. Moore's Law simply states that the density of silicon chips doubles every 18 month.
On a sidenote, Intel's Netburst archicture has turned out to be a failure to reliably increase the PERFORMANCE of the CPU (ironically I'm using one right now), precisely because of the architecture's emphesis on higher clock rate. But other architectures, such as AMD64 and Power are rapidlly shrinking their die and consistently increasing performance.
You've interpreted "a few hundred millionths of a meter" incorrectly. The correct way to do it is:
one hundred millionth of a meter = 1m/100,000,000 = 10nm
Not one hundred millionths of a meter = 100 * 1m/1,000,000 = 100um
it would be nice if TFA had a few facts comparing these to current transistors. Just being "small" isnt good enough. Quite a few things have to also be in the right range to make them competitive, such as voltage swing, current gain, switching speed, reliability, feedthrough and feedback capacitance, and probably more. And it's a bit presumptuous for anybody to extrapolate these things along the same improvement curve as transistors and IC's.
Let me start by saying I am an electrical engineer:
Even if you have perfect conductors and insulators you will still burn power. The gate of every transistor is a capacitor. And you can imagine that the power supply is also a big capacitor. Just transferring charge from one capacitor (the power supply) to another one (the gate of a transitors) uses up energy, even if you have superconductors and perfect insulators. The following math helps:
The energy stored in a capacitor is expressed as E=0.5*C*V^2
So lets take a capacitor which is charged to V=1 volt, and a capacitance of 1 F (this is a silly example but the math is now trivial)
The energy in that capacitor is that 0.5*1*1^2 = 0.5 Joules.
Lets connect it to another capacitor of equal capacitance, with a superconducting wire. The total amount of charge stays constant (Q=CV) So with two capacitors each will have half the voltage. That means we now have 2 capacitors of 1F size with 0.5V on them. Whats the energy now:
0.5 * 1 * 0.5^2 = 0.125 Joules each. Together that only makes 0.25 Joules.
But we started with 1 Joule... Where did the power go? Just charging and discharging something means we move charge from one place to another which takes energy to do so.
So as long as you are moving charge around in a chip, even if you have superconductors, you will still burn energy.