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AMD Lures IBM Veteran to Lead Chip Design
Rob writes "Computer Business Review is reporting that Advanced Micro Devices yesterday said it had hired Jeff VerHeul away from IBM to
lead the direction of AMD's future silicon design. VerHeul's most recent post during his
25-year stint at IBM was head of engineering and technology services. Now, he will lead
the development of all future AMD computing products, including silicon roadmap design
across all AMD's engineering sites worldwide."
The Cell's core CPU is a PowerPC processor. And the PPC is a very good chip - the problem is that IBM decided that it should focus on Power5 and Cell, and neglected the G5 (and had some scaling issue, IIRC). The G5 wouldn't sell nearly as many units as Cell does, and the Power5 probably has a high margin (and is for their own server products). Again, IIRC, IBM tried to sell Apple on the Cell (so they could continue to fulfill their obligations to Apple without keeping up the G5), but Apple felt that the Cell wasn't really a good choice for general-purpose computing.
Athlon wins the prize for brute CPU power, but the real strength of PowerPC is that IBM can design custom chips based on combining PowerPC cores with additional processing elements. This technology is behind Deep Blue, Blue Gene, the PS3, and the Xbox 360.
This kind of chip is hard to program for, but can deliver unbeatable performance per dollar, square centimeter and watt when software is codesigned with the hardware.
AMD and Intel are going in this direction with dual-core, but IBM is already way ahead. For instance, BlueGene is based on a special chip that has two PowerPC cores with an incoherent cache (tricky to program but cheap and fast) and adds an enhanced vector processing unit. IBM is a leader in higher-end SoC solutions (really, anything that gets power from the wallplug instead of a battery.) Lower-power applications are using MIPS and ARM cores instead...
One thing that has been interesting me lately, after reading a series of Anadtech articles on current and near-future processor tech is the possible inclusion of SMT (oft marketed as Hyperthreading by Intel) on AMD cores.
The article mentions the POWER5 chip and it's implementation of SMT and how it behaves with multi-core chips (i.e. how it can devote all threads on one core to a single task, with the other core(s) sharing the workload via SMT) and how it's rather more impressive that the HyperThreading[TM] on Intel P4's, although I'm not a microprocesor guru.
Whilst I can understand AMD's decision not to put SMT in their current processors, with the recent focus on multi-core and multi-threading I think they'd be foolish not to think about it soon, and (as someone not very up on non-x86 chips) it seems IBM's POWER5 is a good base to emulate. Does anyone have any information on SMT implementations in POWER other chips like Sparc and Itanium?
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