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Dynamic Logical Partitioning for Linux on POWER
An anonymous reader writes "Logical partitioning provides POWER processor-based servers with the capability to do server consolidation and optimize system resources. Dynamic logical partitioning enhances this capability by providing control of the allocation of the resources without impacting the logical partitions availability. Linux on POWER supports dynamic LPAR for changes to physical I/O, virtual I/O, and processor resources."
I've worked on it on a few times, and its still a bit buggy, but IBM seems to never cease to amaze me by pulling-out new patches on a daily/weekly basis. With time, this technology will perfect itself, and when it will, it will really rock, for now, I'd still go with a BladeCenter + SAN.
And for once I drool over something I have only vaguely an idea of what it does.
What it does is allow reconfiguration of system resources, such as IO cards, memory or cpu's (or on Power 5 with AIX 5.3, portions of a cpu), etc. on the fly without having to reboot your server to acknowledge them. AIX has had this capability since 5.2.
It's great for being able to juggle your resources on the fly, but it really comes in handy for moving your DVD drive between partitions on a frame without having to reboot. Having to reboot 2 servers just for that is a royal PITA.
They told the same thing 10 years ago about powerpc, and look what has happened.
Target market for Power(5): Servers. No mainframes (as those are a different area), no HPC (horrible FPU/$ performance compared to main competitors), no small servers (PPC970 is more or less dead in the water, and power5 with its horribly expensive MCMs isnt cost effective in the more "normal" enviroment.
SO i _seriously_ doubt "the entire world" will be using power in 10 years. They can be happy if the keep their market share.
HI O WISE PRINCE. WHT TOOK U SO DAM LONG?
I respectfully and completely disagree. The world enjoys using a 64-bit extension to the 4004 architecture. We like using a single-accumulator processor with 3 "general purpose" registers. We adore the massively irregular instruction set, we like saying "push bp/mov bp,sp" every four instructions. We like the whole notion of putting values in certain (and only those) registers, so we can say "repne scasb", or "mul" or "div". The segmented memory architecture and the segment registers, are, in a word, brilliant. The notion of "near" and "far" calls and jumps, and the fact that the segment and offset are pushed in the wrong order is an endless source of delight for us. The floating point unit, and its instruction set, are nothing short of poetry in silicon. The pipelining and branch prediction are the the epitome of efficiency.
In other words, you are just another sadly mistaken fanboy of an inferior processor architecture.
No folly is more costly than the folly of intolerant idealism. - Winston Churchill