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New Server Chip Niagara

* * Beatles-Beatles writes "Sun recently announced their latest release in server technology. The UltraSparc T1 processor, code-named Niagara, has eight computing engines on a single chip, with each core capable of handling up to four tasks at once." With this new processor Sun hopes to get a leg up on the competition. The Niagra chip is being billed as an "eco-friendly" chip because of its low power requirements. From the article: " [...] removing the world's Web servers and replacing them with half the number of UltraSparc T1-based systems would have the same effect on carbon dioxide emissions as planting 1 million trees."

5 of 307 comments (clear)

  1. Better link by Anonymous Coward · · Score: 5, Informative

    Better link here.

  2. Comparisons to the cell? by Anonymous Coward · · Score: 5, Informative

    These processors are a step in a different direction. Like the cell processor, they lack features like branch prediction, have small, very simple pipelines, etc. However, that isn't really all that bad, esp. on some tasks where your CPU is mostly just idling waiting for IO to finish anyway. I wonder if these "simple but gets the job done" CPUs will see an even wider market in the future. As the article said, they are cheaper and consume less power than their competitors

    1. Re:Comparisons to the cell? by Quicksilver · · Score: 5, Informative

      Not really the same thing at all. The cell uses one master to control several specialized units. Niagara is just what is sounds like. 8 cores on 1 piece of silicon. They all are the same and the all can run any Sparc code.... unlike the Cell which isn't compatible with anything and each unit can only work on what it is specialized in.

  3. Re:Apple need this by Anonymous Coward · · Score: 5, Informative

    low power requirements != low enough for a laptop.

    Niagra = 70 watts
    G4 = 19 watts

  4. Re:What about I/O? by Paul+Jakma · · Score: 5, Informative

    The whole point of Niagara is to get higher throughput *despite* memory latencies.

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