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Nanotechnology Gets Finer
An anonymous reader writes "ZDNet reports on a new level of detail found in nanotech construction." From the article: "Japan's NEC Electronics has developed a technology to make advanced microchips with circuitry width of 55 nanometers, or billionths of a meter, the Nihon Keizai Shimbun business daily reported Sunday. Finer circuitry decreases the size of a chip and cuts per-unit production costs. It also helps chips process data faster."
Um? Haven't we had 65nm and 35nm processors for a while? Is this just another Slashvertisement?
The hard limit is around 0.2 nanometers (the size of one atom in
a crystal structure - very roughly of course). The real limit is
that it gets more and more expensive to get closer and closer to
the hard limit, so don't expect anything below 10 nm any time
soon.
Oh, did I mention that you gain less and less from going smaller
because more signal is wasted as heat. Also, solid state physics
really changes around 30 nm (e.g. the concept of carrier mobility
loses meaning - you have to treat each impurity self consistently).
In short, going below even 30 nm is major money (compared with
the currently developed 35-50 nm processes, which are themself a lot
of money to put in production).
For an idea of scale, a ribosome is about 50 nanometers across (it does alot more work than a copper trace, though).
Don't blame me, I voted for Baltar.
There actually is and it has nothing to do with math but physics. Obviously there is a limit when you start talking circuits that are made of single paths of atoms. Even before that there's a leakage that occurs leading to errors. There'd have to be a redundancy to overcome the occational lost electron so you get a deminishing return. There's talk of ways of avoiding the the issue but circuits a few atoms across are likely to be the limit. Anything beyond that will mean working on a sub atomic level and well beyond any known technology.
It will be interesting to see if there is a break from CMOS to some substantially different integrated transistor process in the next 20 years, like there was from bipolar to CMOS in the late 80s. People seem excited about nanotubes, but I don't see how they'll play well with lithography, yet.
We already have 65 nanometer process chips in production. Even this article, after parroting the NEC press release mentions that Intel is building a 45 nm process plant, which is a step further along than "NEC has developed a technology" to make 55 nm chips.
Here is an article from two years ago with an expected timetable for chip process width that exactly matches what we have seen since then: 90 nm in 2004, 65 nm in 2005-2006 and 45 nm in 2007-2008. There really isn't anything exciting about this press release from NEC.
Nanochem promises to allow even tinier feature sizes. The atoms in a molecule are about half a nanometer across, but they can form structures with gaps even smaller. Benzene rings have diameters also about 0.5nm, and can be made in regular arrays as nanotubes. More complex structures can twist these feature spaces even closer, and in vast numbers of regular arrangement. Their production through chemical, rather than mechanical, engineering promises more efficiency, lower cost, and larger production yields.
We are now looking at the nanometer from above, pulling our micrometer structures towards the new horizon. Once across it, we will still use nanometer-scale engineering to produce picometer (and smaller) scale results.
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The hard lower limit is based on the sizes of the atoms involved, but you can't really get very close to a single atom thick without radically changing designs. For example, one of the thinner parts in a typical CMOS circuit is the gate oxide layer. In typical semiconductors, this is composed of silicon dioxide. The problem is that if that is made only a single atom thick, at a given spot you don't really have silicon dioxide anymore; you only have silicon or oxygen. With current designs, you need to maintain a layer that's thick enough to still be silicon dioxide -- i.e. molecule-sized, not atom-sized.
Realistically, even getting close to that is pretty difficult anyway. Even at the present time, the gate oxide layers are starting to cause problems -- the gate oxide layer is supposed to act as an insulator, so no direct current flows through it. In reality, a little direct current will inevitably "leak" through, but in the past it's been pretty small. In current designs, the gate oxide layer is getting thin enough that this leakage current is becoming a substantial part of the total power drawn by the part.
There are ways around that, such as using a different material. When you thin the oxide layer, the conductors connected to each side of it can be smaller, and still maintain the same capacitance. Another way to achieve the same objective is to use a material with a higher dielectric constant (traditionally abbreviated as "K").
Silicon dioxide is also used to insulate between other conductors on the chip as well. Here, you generally want to reduce the capacitance between the conductors though, because increased capacitance leads to increased cross-talk (the signal on one conductor creating noise in a conductor nearby).
Therefore, semiconductor materials people are working in both directions: low-K dielectrics for insulation, that maintain the same (or lower) capacitance between conductors with thinner insulation, as well as high-K dielectrics to allow thicker gate-oxide layers (reducing leakage) while maintaining the increased capacitance of a thinner layer. These, however, typically lead to substantially more difficult (read: costly) manufacturing. Of cousre, there are a lot of other possibilities as well, and each has its own strengths and weaknesses. For example, some designs use strained silicon -- actually "straining" the lattice of silicon molecules in the crystal formation so they're either closer together or further apart. Other designs change the basic wafer construction -- a traditional wafer is simply a layer of silicon. SOI is Silicon On Insulator -- a later of insulation, with a thin layer of silicon over the type. Again, creating the wafer this way costs some extra, but more importantly (at least to the designer) a transistor built this way has something of a memory effect -- the way it acts at any given time depends not only on the voltage applied right now, but also on its previous state. While this may be usable for embedded memory it can be a real PITA for everything else.
Anyway, I suspect the real limit will be mostly economic: a current fabrication facility costs a LOT of money -- around 1 1/2 billion US dollars (non-US residents feel free to assume I really meant 1 milliard Euro).
This expense has already lead to a couple of things: even large companies often can't afford to build a fab on their own anymore, so they often have to form/join some sort of consortium to build a modern fab. Another business model simply separates the companies into two halves: fabless design houses, and then a few companies that just fabricate designs for various others. For an obvious example, neither nVidia nor ATI does their own fabrication -- they design chips that are then built (along with a lot of other people's) by Taiwan Semiconductor Manufacturing Corporation (TSMC). Of course, TSMC ha
The universe is a figment of its own imagination.
Parent needs to be modded up more it is the most coherent comment on the topic posted so far. One minor nit pick - a 65nm\45nm fab costs about $3.5billion see here for the investment required for Intel's Fab 28 in Israel. That's an increase of $1.5 billion on the cost of the existing 90nm\65nm Intel Fab 24 in Ireland .
At least the last time I noticed, nVidia was still using 110 nm. ATI's latest X1 series (R520-based) use 90 nm fabrication, but I'm not aware of these being available as real products yet. The previous generation (e.g. X800) were 110 nm, unless memory serves me poorly.
TI and IBM also produce 90 nm chips. IBM (same page as above) claims to have a 65 nm ASIC production capability on line as well, though I don't know whether they have any real customers for it.
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The universe is a figment of its own imagination.
The universe is a figment of its own imagination.
It's silicon. Silicone is a polymer. With a melting point of 1414 degC, I find it hard to believe you'll get much atomic rearrangement in silicon at 65 degC or whatever your operating temperature may be. The rule of thumb for ceramics is to sinter at about 2/3 the melting point (850 degC for Si) in order to get enough atomic movement to rearrange atoms on any reasonable timescale and densify the ceramic.
One of the key issues in reducing CMOS transistor size is the dieletric properties of the oxide layer. Decrease the size, and you must decrease thickness or increase dieletric constant of the oxide layer. SiO2 is the oxide of choice due the ease with which is is grown atop silicon. Layers thinner than one atomic layer are impossible, and layers thinner than 2-3 atomic layers may not have high integrity. Finding a suitable replacement has proven difficult. Different transistor designs may mitigate this somewhat, but not forever.
Let's say you make a lattice of 1Å (100pm) atoms with bond lengths of 1Å. The 3D geometry of the lattice can bring the atoms into proximity limit by their electrical repulsion and the angles of their bonds. That proximity can be shorter than their bond length - it can be nearly any size or shape. This is how enzymes make active sites with feature details at highly precise scales. Another analogous example, especially at these scales, is how relatively large wavelengths can combine to create differential beat frequencies at relatively much smaller scales. When we make devices out of intervals and gaps, we can get asymptotically small. This is, of course, how we already reach those nanoscales from our mesoscale starting engineering.
:) to both scaling resolutions smaller and aggregates bigger.
:).
What's interesting about these kinds of small features, and chemical processes for their assembly is that they make not only smaller features, but also many more of them simultaneously. So nanocrystalline chemistry offers solutions (pun intended
There is no bottom - hence Richard Feynman's famous lecture title, which I stole with pride
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