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Sun Open-Sourcing UltraSPARC Design
AKAImBatman writes "While everyone was busy with the holiday season, Sun Microsystems quietly announced the start of the OpenSPARC project. Unlike previous CPUs that were based on the "Open" SPARC specifications (such as LEON), Sun is releasing the complete Verilog source code to their latest and greatest microprocessor. Their current time frame for releasing the source code to the public is in March of 2006. Given their success with the OpenSolaris project, it seems that this is likely to be more than just vaporware. So get out your Virtex FPGAs and your Verilog compilers, and let's get ready to hack some hardware!"
I'm all for their ideas on OpenSolaris, but this may be going a bit too far. Didn't they open Solaris to sell more hardware? I'm pretty sure a company that doesn't make money is like a species that doesnt reproduce... dead.
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These new servers absolutely rock, and at superb prices.
I once had the pleasure of a 4-way Opteron v40z with a development version of 64-bit Solaris 10. It was a screamer, especially compared to our 4-way Dell P4 Xeon box, and 64-bit.
It was plenty fast enough to host 4 zones and several developers working on KDE, gcc and all manner of other stuff.
At last, Sun looks like it's turning the corner (despite the best efforts of some of its PHBs - no names mentioned).
Good luck Sun.
I'm doubting that Sun synthesizes verilog to get a 2 GHz processor. Their CAD teams must create custom transistor designs and use formal equivalence with the verilog to prove correctness. Synthesizing the entire processor must require more than one Virtex4 or Stratix-II part, so I can't see people really doing anything with this other than proof-of-concept systems. You could possibly cannibilize parts of the design to make it fit in an embedded system (that's the only speed you'd be able to get out of it). I... dunno. There must be a reason.
:-)
The best part in my mind? Think of all of the processor design classes in upper-level EE courses that are going to get a whole lot easier!
I'm also really surprised if the entire SPARC processor is written in synthesizable Verilog. I would think that this processor would contain numerous asynchronous parts (difficult to synthesize properly) and plenty of custom hard macros (designed at the transistor level).
You know, I'm not sure how much of an impact this will have. There are other sparc manufacturers, but no one really seems to take notice.
It's a little bit early to say yet, but if all the "design source, verification suite and simulation models" are released as open-source (as TFA said), and if the license would allow design and manufacture of systems based on that chip without paying an arm and a leg (which TFA didn't mention), I'd say: "Woohooo!", and I'd say this for all the developing countries, including China, India, etc.
And I hope this will "sparc" a revival of the sparc acrhictecture!
HP should've done the same with the Alpha architecture instead of letting it die a forgotten death. What a shame!
Anyone can make changes to improve the design. The changes are likely to be specialized tweaks to make one task run really fast rather than a faster general purpose processor. And depending on the license everyone gets the benefit of the change.
Say someone comes up with an algorithm that would run ten times faster if only there were just a few more registers or if there were a single instruction that would perform some combination of math on all the registers at once.
Certainly not as DIY as hacking the Linux kernel but this is something someone could base a business on.
Excluding the fab, it takes an enormous amount of design and layout effort to go from RTL to masks. SparcT1 is not a purely synthesized design. Even if it were, the tuning required to make synth work is a nontrivial effort requiring a significant tool foundry.
I suppose that once we have open source versions of: schematic capture, synthesis, floorplanning, layout, timing, validation, and mask generation, then we can focus on an open source process and an open source fab. Not bloody likely!!!
I think the biggest benefit here is that now both hackers and Universities now have a REAL architecture to study in their classrooms. I'll definitely be on the prowl for resumes of students who studied real microprocessor Verilog in college, and not simple ISCAS circuits or architectures from the 1980's.
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I'd be surprised if they release the codebase for the entire chip. There is alot of industry secrets that go into processors that are not patented. By giving this away, they'd give IBM and HP the abilitity to analyze the performance of the chip with a fine tooth comb. It only provide more FUD for HP and IBM to throw at them.
The interface portions of the chip to be probably be opened up. Mainly to allow other companies to design chipsets for their new system.
I would like to see where they go with this. Software is a great thing to opensource because changes can be make with little effort and it is very cheap to verify your changes worked. Chip design on the other hand is extremely expensive, with slow turn around times and difficulting in debugging. Not only do you have to worry about the code, but how to design it properly for the process that is being used to fabricate it. Opensource is all about turnaround time, and chip design currently can not support that. Now if someone could create a extremely high density reprogrammable chip (500M gates) then all bets are off.
However, this will be a great learning experience to see any code they provide. It will give student and people in developing nations a chance to learn what goes into a 'high' performance chip design.
At Sun's quarterly announcement today, their benchmarks are showing the T1000/T2000 servers at 3 to 4 times the performance/watt of any Xeon or POWER5 server. These new servers ought to be web hosting monsters. I also wonder if they would make good Sun Ray servers (lots of ram and responsiveness via multiple cores might be good for lots of GNOME sessions).