Slashdot Mirror


Reduce Transistor Power Consumption

revelCyllufyalP writes to tell us that University of Kentucky researchers have discovered a way to reduce the overall power consumption of transistors. From the article: "In order to improve computer chips' performance, transistors' size and gate insulators have to be continuously shrunken so that more components can be packed into a single chip. Computer chip producers were hitting a wall in downscaling the transistors and gate insulators because of their inability to reduce the leakage current of the existing gate insulators. This new technique will help the chip producers to develop more powerful chips with low-power consumption."

6 of 124 comments (clear)

  1. Woohoo by matr0x_x · · Score: 4, Interesting

    This may not sound like that big a deal, but let me assure you this is very significant to wireless infrastructure enhancement. One of the biggest limiting factors in wireless devices is power consumptions, so this is great news for the industry!

    --
    LINUX ONLINE POKER: Linux Poker
  2. How do you reduce tunneling current? by Beryllium+Sphere(tm) · · Score: 4, Interesting

    The press release says they're getting several orders of magnitude less tunneling current through gate insulators. But tunneling happens because some portion of the electron's wavefunction extends to the other side of the insulator. Whst are they changing that would affect the physics? Or are they fixing a different kind of leakage and getting the press release wrong?

  3. Where's the news? by Anonymous Coward · · Score: 5, Interesting

    As probably one of the few semiconductor geeks on /., I have to say: Where's the news? Gate dielectrics are always made with rapid thermal processing on current technologies. Basically, stick a wafer in a chamber, flow some gas, turn on some super-high intensity
    lamps, heat the wafer to >1000C for a very brief time, grow a few atomic layers of silicon dioxide (or some variant that includes nitrogen), turn off lamps, cool wafer, take it out of chamber.

    From what little info is in the press release, it doesn't sound like they're doing anything revolutionary, so I'm curious why they claim they can reduce gate leakage by so much.

  4. It is already done, old news by karvind · · Score: 4, Interesting

    Gate oxides in current microprocessors are around 1.2-2 nm and are grown using RTP (rapid thermal process). A furnace oxidation is too fast. So yes industry already uses rapid thermal anneal (as suggested in TFA) for their gate oxides. Can anyone tell how is the new ?

  5. PlayfullyClever, eh? by Ospeovedizer · · Score: 5, Interesting
    So, did ScuttleMonkey not notice that the submitter's name was PlayfullyClever backwards? The one whose website says that the vast majority of /. posts are "blatantly plagiarized"? Although the news seems real enough to me, the submitter's name and website raised some pretty big alarm bells, especially since their site now says:
    "okay, so we are going to win slashdot again, this time with a different game plan, keep your eye out for our new name.. it is VERY playfully clever."
    Hmm... As I said, the news seems real enough, but the submitter is a fake.
    --
    "We demand rigidly defined areas of doubt and uncertainty!" - Vroomfondel, H2G2
  6. Re:size vs heat by soundsop · · Score: 4, Interesting

    Some clarifications:

    Short-circuit current is only responsible for 10-20% of switching power. The rest is dissipated in the transistor through charging and discharing all the nodal capacitances (due to transistor gates, transistor diffusions and wiring capacitance). Since typical circuit styles are non-adiabatic, this charge/discharge power component would not go away even if we could completely eliminate short-circuit currents.

    Making transistors smaller certainly reduces their gate capacitance but it also reduces their current drive by the same proportion. These two effects cancel each other out! So how can transistors get faster from generation to generation?

    Transistors get faster by increasing electron mobility and/or increasing gate capacitance per unit area and/or reducing diffusion junction/sidewall capacitance per unit area/perimiter and/or reducing (local) interconnect capacitance since smaller transistors are closer together.