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Under the Hood of the Xbox 360
An anonymous reader writes "IBM DeveloperWorks is running a behind the design story for the making of the Xbox 360. The 360 has but a single chip with 165 million transistors for it's CPU " From the article: "This chip is in fact a three-way symmetric multiprocessor design. The three PowerPC cores are identical, except that they are physically reflected through the X and Y axis. Each of the CPU cores is a specialized PowerPC chip with a VMX128 extension related to (and partially compatible with) the VMX instructions in the G4 and G5 CPUs. The three CPU cores share a 1MB Level2 cache. Each processor has 32KB each of data and instruction Level1 cache. The chip's front-side bus/physical interface has a 21.6GB/second bandwidth, and runs at 5.4GHz."
This is probably a JTAG block. Depending on what it's built for, you get:
- instruction single-step
- register and memory peek/poke
- control suitable for burning on- and off-chip flash/eeprom
- trace buffer that contains the most recently-executed opcodes
- breakpoints
- access to profiling and instrumentation registers
JTAG is a serial protocol that runs much, much slower than the core -- but it's an extremely nice way of getting into a running chip and poking around.
It's probably the JTAG debug logic. Most modern CPUs use a JTAG port (full-duplex, multi-device serial port) to provide access to internal CPU state, as well as providing hooks for starting and stopping the processor.
/ 3675.html
JTAG is a hardware test standard, but chip vendors define their own extensions to it to provide software debug hooks. Most PowerPC chips use what's called the Common On-Chip Processor (COP), which is controlled through the JTAG port. The specific details of COP and its implementation on each chip is proprietary, and usually only available to IBM, Freescale, and a few select tool vendors with NDAs. Here's a link to some more information on PowerPC COP:
http://www.elecdesign.com/Articles/ArticleID/3675
Games often have far smaller cache requirements than many other applications, and as a result, it is preferable to go with a higher speed cache and higher CPU speed than a slower but larger cache/CPU.
:)
The Celeron in the 300A era are one of the best examples of this. They had half the cache of their Pentium III counterparts, BUT the P3 cache ran at half the CPU speed while the Celeron cache ran at full speed. The Celeron's performance was crap despite the faster cache for many applications (including server machines and most office applications) due to its smaller cache, but gamers discovered that for games, the situation was exactly the opposite - clock for clock the Celeron was significantly faster than the P3 due to the fact that most games in that era could fit almost all of their rendering pipeline within even the Celeron's small cache. Rare cache misses and twice the cache speed = much better performance. It also happened that that on-die cache allowed the Celerons to be overclocked like crazy, a significant added bonus.
The Xbox 360's CPU takes the whole idea much farther. While most desktop CPUs are designed to perform well over the widest range of situations (with some tradeoffs always being evident - note that Athlons eat P4s for lunch in many cases such as games, while Athlons do actually lose most of their advantages in performance per clock cycle when performing video compression and decompression because most video codecs don't have significant amounts of branching resulting in pipeline stalls from branch mispredictions.) The Xbox 360 CPU goes a step further by optimizing for one thing and one thing only - gaming. Instruction reordering which is critical in most desktop CPUs turns out to be not as necessary for gaming (specifically graphics rendering), and as a result the 360 drops instruction reordering capability completely in favor of having multiple cores at a low cost. (Instruction scheduling takes a LOT of die space in modern CPUs compared to the size of the rest of the CPU core.)
retrorocket.o not found, launch anyway?
Hate to burst alot of bubbles, BUT:
0 -2.ars/2
The Xenon CPU IS NOT the same as 3 G5's all on one chip! Read the arstechnica article here:
http://arstechnica.com/articles/paedia/cpu/xbox36
Basically it says: "The basic idea behind both Cell and Xenon is to make the execution core less complex by stripping out hardware that's intended to optimize instruction scheduling at runtime. Neither the Xenon nor the Cell have an instruction window, which means that these two processor designs largely forget about instruction-level parallelism. Instead, instructions pass through the processor in the order in which they're fetched, with the twist that two adjacent, non-dependent instructions are executed in parallel where possible."
This means that standard PPC code (OS X, etc) WILL NOT RUN on this. This is also the reason that IBM is selling these things at only $106 a pop to M$. Have you checked the prices for SINGLE CORE G5s for Apple? Their like $600-700 a piece! So, I am guessing that stripping these down makes them much easier and therefore faster and cheaper to mass produce, and therefore the price difference.
Anyway, there are reports that only one core is availble to intitial game developers, and one of the cores is strictly for M$ bullshit content protection TC such as the hypervisor, etc.
Not to mention from the article:
Microsoft and IBM engineers worked together during the definition phase of the project to specify a design to satisfy the constraints of a mass-produced consumer device
Sounds like a shitload of TC shit build right into the chip, so I am NOT holding my breath for linux to be ported to this (not that I wouldn't be thrilled to see this). Cetainly not when the port to STI Cell architecture has been under dev for what, over a year? Damn, can't wait for PS3 release.