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Who Makes Custom Chips?
toybuilder asks: "I have an idea for a neat consumer product that could benefit greatly from a really simple bare-die chip to reduce cost and size. I took a VLSI and chip design class back in college about 10 years ago, so I know how to design the circuit I want in CMOS. Now, I'm sure there must be fabs for older-generation designs (maybe in China/Taiwan) that I could have such a chip made -- I've seen bare chips in musical greeting cards and in tiny toy gadgets. How do I go about making my chip design into reality if I only want to make a fairly short run (a few *chips* during development, and maybe a 6" wafer's worth of the final design)?"
Spot on. If your run is 1 wafer, it would be hideously expensive to build the masks. Custom chips only make sense when the volume is large, since verification and mask creation costs give it a large up front cost. FPGAs are a good comprimise, cheaper than a processor and without the up front costs of a custom chip.
I still have more fans than freaks. WTF is wrong with you people?
You want MOSIS. Providing small volume chip fab services (via short ganged-mask wafer runs at flexible mainstream fab houses) for decades now, Mosis is exactly what you want if FPGA and a programmable microcontroller aren't what you really need.
If you want to attempt it, MOSIS does small run fabrication by batching up small runs onto a single wafer and running them through commercial fabs like IBM and TSMC. The prices aren't out of reach.
However, you should remember from the VLSI class you've taken that it may take several runs before getting anything usable. Unless your design has some aspect that makes using a FPGA infeasible, you'd probably be better off with the FPGA. As I recall, a couple of FPGA vendors can also do conversions from FPGAs to hard-wired ASICs if you desire it later.
I used to work at SNF. Industry and small businesses were also allowed to use the lab. I has some very modern equipment but it is mainly for prototype. Once you have a working sample it then can be sent to a fab house for a production run if you get funding. It is not exactly cheap but a small project could be done w/o alot of investment. It all depends on how complicated your process is.
I have secretly hidden some mispelled words in this post. Can you find them?
Almost every reply seems to think that the only chips in existence are digital. If you are thinking of a digital design then, as the others said, FPGAs are the way to go - certainly for prototyping.
If you need an analogue device or want chip scale packaging of your device, then an asic would be more appropriate. It is possible that FPGAs are available in very small packages but I'm not very up on that.
If you're in Europe, the Europractice scheme provides access to Multi-Project Wafer (MPW) runs to reduce overall fabrication costs. They also provide the software and design kits that allow you to make your designs.
My price breakdown for a 10sqmm chip in the AMS C35B4 process (0.35um, 4 metal, 2 poly, high res) with 20 devices in CSOIC28 packages:
Full Europractice membership (annual): €900
Cadence IC package single license: €1800
Cadence IC package maintenance (might not be applicable for the first year): €1150
10sqmm of AMS C35B4 silicon @ €720/sqmm: €7200
20 packages @ €52/package: €1040
Total: €10,940 or €12,090
Non of the prices include any local taxes.
They also do low volume production, but I don't know anything about the pricing.
So how to bring that down? You could save €1800/€2950 on software by using free alternatives such as on this
page. You'd have no end of problems with design rules and layout vs. schematic verification but it would be possible. Normally I'd say allocate two months of hard graft at the very least using the normal tools and with support from someone who knows what they're doing. With inadequate tools (no design rule check/layout vs. schematic) you would have to at least double it and you still might have errors.Don't be influenced by your opinions of current design processes. We use a 0.35um process all the time. It's perfectly adequate for what we want to do - in fact in many ways it is better than smaller processes for us. You could save a lot of money by going to a coarser process such as the AMIS 0.7um (2 metal, 1 poly) at €360/sqmm or the AMIS 0.5um (3 metal, 1 poly) at €420/sqmm - both with a smaller minimum size at 8sqmm. Silicon cost would then be €2880 or €3360 compared to €7200. 8sqmm is quite a lot really.
Ultimately, you need to decide what you need. If you need analogue circuitry but don't need linear capacitors, go for the cheapest process. If you do need linear caps, you'll have to use a process with 2 poly layers. If you want digital as well, go for something finer and with more metal layers
Do you have any better hostages?
You might try looking at the Cypress PSoC. It offers a small RISC-y micro coupled with an array of analog and digital blocks that can be configured for your application. They're low power, available in small packages, and are very cheap. Apple has even started using them as a single-chip solution for their new touch wheel controller.