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Moore's Law Staying Strong Through 30nm
jeffsenter writes "The NYTimes has the story on IBM with JSR Micro advancing photolithograhy research to allow 30nm chips. Good news for Intel, AMD, Moore's Law and overclockers. The IBM researchers' technology advance allows for the same deep ultraviolet rays used to make chips today to be used at 30nm. Intel's newest CPUs are manufactured at 65nm and present technology tapped out soon after that. This buys Moore's Law a few more years."
At what point does BUSS technology break down? Figured this was where to ask.
Physics is like sex: sure, it may give some practical results, but that's not why we do it.
I am too lazy to learn these things from scratch but would anyone cared to tell us what's the theoretical minimum width we can go before eletrons starts jumping wires? I hope it's not 5nm.
"This buys Moore's Law a few more years."
I've heard that more than a few times.Isn't that why it's a law? It seems like every 18 months or so, Moore ends up almost petering out (kind of like apple...) and there ends up being a redeeming breakthrough that keeps it around.
If it wasn't a law, we'd just call it Moore's hypothesis, or Moore's pittiful attempt at justifying an upgrade. I remember the day when 50Mhz was the theoretical limit for speed and then they got the grand idea of putting a heat sink on the chip.
--pete
since RIT has been doing 26nm. http://www.physorg.com/news10755.html
I believe Moore's Law (or, rather, the modified version about processor speed rather than transitor count) will transition to a new regime soon - that of "average" exponential improvement in the form of a punctuated near-equilibrium.
I believe that the chip industry will have to shift paradigms as the limit of a technology approaches and during these shifts there will be a period of relative nonimprovement as new techniques are refined, implemented, and large scale facilities are built.
There's so many promising technologies on the horizon (photonic computing, three dimensional "chips," quantum computation) etc, but the transition to each will be very bumpy, not at all smooth like the last 40 years of refining two-dimensional semiconductors.
As times change, what we know as Moore's law will change with it. It's likely that the "average" improvement will continue to follow the law more or less (considering that it is driven more heavily by economics than technology). Computers will continue to get faster, cheaper, and able to do things we wouldn't have thought we needed to do before.
So your computer will be nice and fast, just not any of your applications...
Z.
While the smallest chunk of silicon we could lay down would be one atom of it, there are things far smaller. In fact you can go something like 26 more levels of magnitude smaller before you start reaching the feasable limit of measurable existance. And yes, subatomic particles could theoretically be used in processors.
The process designation refers to the the distance between the source and drain in the FETs (transistors) on a processor. Keep in mind that this distance is by no means the smallest thing in the processor - the actual gate oxide layer is tiny by comparison, with Intel's 65nm process having only 1.2nm of the stuff. That's less than 11 atoms thick.
Found this on a thread at bit-tech.net forums.
"Let us raise a standard to which the wise and honest can repair" - George Washington
You can trust me on this. I have access to that interweb thing.
All this means is that AMD and Intel have to license the technology from a competitor. That's hardly good news for them, and it probably means higher CPU prices for us.
This isn't good news at all.
What happens when they get to -1 nm then? Can they keep going smaller?
sPh
Moore's law is about the number of transistors on a chip. It states nothing at all about speed.
I believe posters are recognized by their sig. So I made one.
Well, if the gate layer is the smallest thing in the transistor and it is 11 atoms wide and 1 atom is the smallest measure, then smallest transistor theortically possible is 65nm/11 = 6nm
You are confusing dimensions. When intel refers to 65nm processes, they are talking about length and width ability to carve out features. Oxide layers "thickness" operates in the third dimension ("height"?) to provide resitant layers. It is much smaller then 65nm. Actual atoms are about 200 picometers in "width".
From:
http://news.com.com/FAQ+Forty+years+of+Moores+Law
This is not about mhz ratings, though for a while these were doubling along the same rate as transistors per square inch were. Moore's comments were about integrated circuit "complexity" minimum component costs, which, if you are talking about transistors, has remained reasonable accurate. If you are talking about mhz per dollar, then you're going to find this is not accurate at all.
Long story short, if you had a 2 ghz machine in early 2003 and you're wondering why you aren't on an 8 ghz machine now, it's because mhz ratings have NOTHING to do with Moore's Law. Which is why I suggest referring to the Wiki entry on it.
Also important is Kryder's Law for HD storage capacity. Within a decade or two we may be able to store all creative works ever created on one drive.
Case in point: Hard drives increase a thousand-fold in storage space every 10.5 years. In 1996 I purchased a Compaq computer with a 1 gig drive. That was an insane amount of space at the time, but now, 10 years later, it looks like I may be able to purchase my first TB drive soon.
* Lines are 2-D thingies, but conductors are 3-D. Your etching technology has to get X times better to keep up with the line-drawing technology.
* Same thing with the active components. If you try making the transistor half the old linear dimensions, you have 1/8th the volume of active silicon. This leads to all kinds of problems with leakage and power handling capability.
* A line that's half as wide and half as thick has four times the resistance per unit length, and 1/4 the current-carrying capacity. You can try using a better conductor, but once you get to using copper, you're done.
Why do I get the feeling that you actually have no idea what you are talking about, and neither do the people who modded you up. Etching, depositing, and lithography all go hand in hand when talking about an Xnm "process", therefore your comment about "thinner lines", in fact, makes no tangible sense. Lithography is the most difficult to shrink, not etching, so I'm really failing to see your point. It has been the main technical hurdle for the past 10 years.
Furthermore, the "conductors" in a processor aren't nearly as dependant on size as the silicon-feature construction. You can have an extremely layered chip with larger conductors if need be (and modern chips are), so both comment #1 and #3 are reasonably meaningless.
As for comment #2, yes, you are right: the "smaller transistor" problem is very well understood and it's the reason it takes so long to construct smaller and smaller processes, because the physics and effects must be taken into account. Not all transistors on a chip are the same size, nor can all transistors be shrunk. There is a reason that Intel doesn't slap it's PentiumIV plans into the new 30nm machine, and out comes a new chip. They have to go through and make sure that all the transistors that can be shrunk are, and none of those that cannot, are not. This is a reasonably non-trivial task, but it is not impossible, nor a "large can of whup-ass".
(PS: Thanks for the math lesson about 2d vs 3d in part 1. You might want to recheck part 3, with that in mind.)
If you are simply talking about Moore's Law in terms of processing power, there are other places to gain improvements rather than just compactness of chips. There is also parallel processing technology, which is still steadily improving.
There are many important algorithmic problems that are inherently serial. Some things are mathematically impossible to parallelize. Also limitations caused by enforcing cache coherency, communications interconnects, and resource access synchronization/serialization create bottlenecks in parallel systems. The astrophysics simulation code that I paralellized is almost entirely math operations on large arrays (PDE solving), however there are diminishing returns past 48 processors due to communications latency. Better programming techniques can push the limit of this, however it is difficult to design software that mitigates the effects of this kind of latency without many man-hours spent to handle it.
Then, far off over the horizon, there's the possibility of quantum computing, which would make for a rediculously huge surge in processing power all at once.
I mentioned this in my post, however there is a bit of a catch. Quantum computing, practically speaking, is only useful for certain problems - problems that are "embarassingly parallel." QC does not help with fundamentally serial problems, and is likely to be impractical beyond a critical number of qubits, due to quantum incoherency, even quantum error correction can only stretch so far. Great for cryptography/number theoretic operations, and probably many optimization problems (scheduling perhaps?) but certainly not for standard computation. Problems (like database queries) that require large amounts of data to be stored in a quantum coherent fashion are unlikely to be practical.
"That's fundamentally how Moore's Law works: as soon as the current paradigm starts to get maxed out, we simply shift to another paradigm."
Ahh, but that's just it - there is a cost to the switch in terms of both time and money. What I am saying is that yes, we can continue to change paradigms whenever we hit a limit, however these transitions will be very expensive and will cause "delays" during which little improvment on shipping computer technology will be seen.
The Electrons in your transistors are "blurry". When the walls of their potential wells (i.e. the width of the wires) get to low, they will start to tunnel between them in a number that is inacceptable for the operation of a logical circuit. Note that tunneling probability is proportional to something like e to minus the potential well height, so there is no critical limit, rather a smooth transition from "no problem" to "show-stopper".
So the real question here, which is left to the audience, is at what width do we get a real problem with tunneling currents. (I assume that on contemporary CPUs, the effect is already measurable, yet correctable).
There are several reasons why the industry is focused on smaller. I do not work for a semiconductor manufacturer, so some of my information may be a little off.
1) Defects and Yield. Most processors are manufactuered out of silicon wafers 300 mm in diameter. The wafer is very pure silicon (before they start doping it), and the crystal structure is one of the most perfect and regular that humankind has ever been able to produce (at least on a large scale). The industry doesn't do this merely to be perfectionist - it costs a LOT of money and infrastructure to do it - but simply because defects in the crystal structure and silicon purity result in a non-functional chips. The statistics and probabilities behind how many defects get scattered on a wafer, and how many potentially useful chips do those defects knock out has been heavily studied by the industry. The yield that one gets from a single wafer that has many chips on it is a function of defect density and chip size (and other things). A larger chip naturally has a greater chance of having a defect than a smaller chip. There isn't much more that the industry can do to reduce the number of defects on a wafer. In order to increase yield, one of the things the industry banks on is decreasing the chip size. The yield for, say, op-amps (which are very tiny chips) is much higher than for full-blown processors.
2) Signal Distance. The upper limit of speed for an electronic signal in a chip is the speed of light. That's really fast, but not infinite. In fact, compared to the clock speed of the chip itself, the speed of light becomes significant. The speed of light in a vaccum is 3 * 10^8 m/s. In one nanosecond, light travels 30 cm. For a 4 GHz processor, light can travel only 7.5 cm between clock cycles. In truth, the electronic signals in the chip travel slower than that. So, the distance between various parts of the chip become significant. For a chip as large as several inches, it can take quite a long time, many clock cycles, for bits to make it from one end to the other. Wasted clock cycles = reduced performance. So, in order to continue increasing performance, the industry has worked very hard to keep the size of processor chip very small, so that it takes very little time for signals to travel across it.
3) Power. It would take a while to explain the physical reasons behind it (see an VLSI or semiconductor textbook for a full analysis), but the operating voltage of a transistor goes down as its physical size goes down. It used to be that 5 V was the working voltage of most all transistors. Then it moved to 3.3 V. Nowadays, the core voltage of most processors is around 1 V. As the operating voltage has decreased, so too has the power dissipation per transistor. The deceasing feature size of transistors and photolithographic techniques is largely to thank for this. The reason that processors now dissipate such a large amount of heat is that, even though the per transistor power has decreased, the number of transistors in the chip has increased more rapidly. If one tried to make a P4 chip using 350 nm techniques (which used to be the standard feature size les than a decade ago), the chip probably would dissipate many hundreds of Watts.
4) Speed. One would again have to check out a VLSI textbook for a full explanation, but (physically) smaller transistors can switch states faster than large ones. While clock speed is far from the be-all, end-all measure of processor performance, it is generally true that faster transistors result in faster performance (hence the whole notion of overclocking). Using the szame "P4 made using 350 nm technology" example, it would be impossible to run such a chip at anything close to 4 GHz. In fact, I doubt you'd be able to get it to run at even 1 GHz - the transistors would simply be too slow. I don't recall exactly when 350 nm was the standard technology used by the industry, but I imagine that you'd find it coincided roughly to the times when chip speeds were mea