A First Look at AMD's M2 Platform
Knight Thrasher writes to tell us that Tom's Hardware has an interesting first look at AMD's AM2 platform. From the article: "While Intel will be answering later this year with its Merom/Conroe processors, AMD officially says that the introduction of its AM2 platform and DDR2 memory support in the second quarter of this year will be able to maintain its current lead. Unofficially, we know that AMD will launch six dual-core and two single-core AM2 processors on June 6 - later than initially expected but well in time for Intel's Conroe, which will be introduced in September. Tom's Hardware got its hands on a stable engineering sample of an Athlon 64 X2 4800+ for Socket AM2 and will publish benchmark results as first as a first impression of the new Socket and processors tomorrow."
So, Slashdot is now referring to articles which will be up tomorrow?
I thought DDR3 was the future?
I read that it is expected late 2006/early 2007 and Samsung claims it'll be 2x the speed of DDR2 and it'll operate at 1.5v (less power consumption).
I know NVidia is already using it on video cards...
[Fuck Beta]
o0t!
You won't be getting FB-DIMM support with the M2 socket, it's for their consumer level/low-end workstation (single CPU Opteron) segment.
Socket F/1207 for their server chips is rumored to support FB-DIMMs as well as some other neat-o stuff.
Don't get me wrong, I love the idea of using FB-DIMMs since it would just mean changing out the motherboard and not also the processor, but with the relation between processor and memory interface, I don't see it as being a big issue. Especially considering the fact that DDR2 is available and about equivalent to DDR in prices (about $150 for a 2x1GB DDR400 or DDR2-533 matched pair, as of two seconds ago at Newegg), whereas FB-DIMMs are unavailable right now and will probably start off pretty expensive compared to what's out.
How are sites slashdotted when nobody reads TFAs?
Cool, Now I'll be able to afford a top-of-the-line Socket 939 system
in a few months for Half Price! Hooray for the inexpensive future.
AMD hasn't changed sockets just for kicks. The 754 to 939 transition was to add extra pins for the dual-channel memory controller. The AM2 socket transition will be to add support for DDR2 memory. These things required not just extra pins, but extra traces on the motherboard. Moreover, the traces have different timing characteristics because of the change in memory type. So even if AMD had used a socket with extra pins, old motherboards still wouldn't have the right lines to connect them to.
A deep unwavering belief is a sure sign you're missing something...
You're overlooking the frequency difference; because FBD is point-to-point, it can run at 5GHz or more, compared to a mere 800MHz for DDR2. Thus with an equal number of pins, FBD gives much more bandwidth.
Yes, with FB you can put all your DIMMs on a single set of signal lines.
That's not how it is used, so I'm not sure why you are emphasizing that. IIRC, Blackford systems have 4 FBD channels (using fewer pins than two DDR2 channels).
I thought FB-DIMMs were merely buffered (as the name implies).
Nope, they're not. They're arranged in a big serial shift register.
The problem with this? Latency goes up as you put in more DIMMs. Why? Because data from the 4th DIMM has to pass through (not just by) the 3rd DIMM, 2nd DIMM and 1st DIMM to get to the CPU.
Sound familiar? It's just a retread of RDRAM.
No thanks. Intel boned themselves with this before. If they want to push this, they better get ready to take a backseat to AMD again. DDR outdistanced RDRAM handily on performance and price/performance, I'll be surprised if things are any different this time.
I hope you enjoy your higher clock speeds, you'll need them to try to get your latency down to managable and your bandwidth up to normal. I mean, with 1/4 as many data pins (I assume the 28 data pins carry only 16 bits of data at once, vs 64 of DDR/DDR2), you're going to have to go 4X as fast just to match the bandwidth and latency of a regular system. And as soon as that 2nd DIMM is put in, you're behind on latency and you're going to have to play catch up.
http://lkml.org/lkml/2005/8/20/95
A video-card? Allow me to clarify: Video-cards routinely have 256bit mem-buses right now, and they have RAM that runs at around 1GHZ, giving them metric assload of memory-bandwidth. In order to achieve that, they use RAM-chips that are soldered right on to the board, and they have hefty heatsinks. What if processors had something similar?
Processors would be sold in cards not that different from vid-cards these days. They would connect to a slot, and they would fhave the CPU, and attached to that CPU would be about 512MB (maybe more, maybe less) of very, very fast RAM on 256bit bus. Of course, it would cost a bit, but not more than video-cards do today (I bet that GPU's are more expensive to make than CPU's are). Yes, there are issues of memory-expansion, but what if there were regural DDR2 mem-banks attached to the northbridge on a "normal" 128bit bus that could be used for additional memory?
If we had a SMP system with this kind of setup, it would offer A LOT of bandwidth. Each CPU would have very fast RAM attached directly to it. And they could access the RAM attached to the other CPUs. AND they could also access the RAM attached to the northbridge.
Or maybe if they used the locally attached RAM as L3-cache? 512+MB of cache, anyone?
Is this idea completely stupid, or does it have some sense to it?
Lesbian Nazi Hookers Abducted by UFOs and Forced Into Weight Loss Programs - -all next week on Town Talk.
AMD just licensed something called zram which will allow them to bundle oodles of L3 cache in the near future.0 216034806.htm
http://www.geek.com/news/geeknews/2006Jan/bch2006
First off, you left out several currently used Intel sockets, including the mobile one(s). The AMD side has been very simple: Budget (754), Mainstream and Workstation (939), Servers (940). That's it. It's not hard. The mainstream S939 offering spans everything from 1.8GHz super-cheap CPUs to dual-core opterons and monster (2.8GHz) FX62 CPUs. If you can't get an upgrade out of your S939 board you're not planning it right. Mobile? Shit, you can put your low-wattage Turion64 in (almost) any old 754 board! How's that for an upgrade?
Heck, I've got a S939 board which also supports AM2 via an add-on daughterboard. For me, that's a really pointless solution considering the overall price of switching CPU and memory, but hey, it's there if you want it. If this works out, the maximum CPU that I can upgrade to on this S939 board hasn't even been announced yet, maybe not even planned.
What socket will the new Intel Monroe stuff use by the way?
Hey hey, what about Socket 603/604 for the Xeons?
Just "gittin-r-done," day after day.
See link:
http://www.theinquirer.net/?article=15189
What happens is on each clock, the 1st DIMM transfers its data to the CPU. The 2nd DIMM (if there) transfers its data to the 1st DIMM, the 3rd DIMM (if there) transfers its data to the 2nd DIMM, etc. Thus each DIMM gets the data from the next DIMM, puts it in a buffer, thus regenerating the signal electrically and emits it upstream on the next clock. You could call this "daisy chained". This limits how far each DIMM has to drive its data, which is why FB-DIMMs can claim better electrical characteristics.
What this means is to get data from the 3rd DIMM, it takes 3 clocks just to get the first bit of data (presumably 16 bits) to the CPU. The "good" news is that since this system is (semi-) serial, the clock has to be very high already, so this latency is somewhat mitigated.
FB-DIMMs are point to point, but the point-to-point doesn't mean each DIMM connects to the memory controller, it simply means each DIMM is only on a bus with one other DIMM (well, one upstream bus and one downstream bus). Each DIMM forwards data along these busses in both directions. But again, there is no way for the 3rd DIMM to get to the memory controller without going through (and not just by) the 2nd and 1st DIMM first.
Your extension of my argument to PATA vs SATA just underscores your misunderstanding. My concern is with the latency of intermediate forwarding of data. SATA (well, the version in regular use) doesn't even allow you to attach multiple devices to a single bus, let alone have the devices forward the data to the head. Note that PATA allows multiple devices per bus, but it is a true bus, in that the data from the far device just goes by the near device, not into it and back out.
SATA is taking off due to connector costs and cable routing in the case. RAM doesn't face cable routing difficulties. It does face signal routing difficulties, but these only need to be solved once per motherboard design at worst, not once per installation as in cable routing. In addition, the signal routing complexity is much higher for ultra-high speed busses and thus the problem of signal routing will be solved the same way for FB-DIMMs as for DDR or DDR2, which is one company (Intel) will make a reference design and the other motherboard designers will just leave those signal lines alone and add other signals in the I/O area where they want to put on additional SATA RAID controllers. And in regards to connector costs, FB-DIMMs don't change the DIMM connector and thus don't reduce the cost of the DIMM connector. So I don't see a parallel here at all.
Finally, as to DIMMs and busses being forward compatible forever, it's just not going to happen. You'll have the same problem you did with SDRAM (or DDR or RDRAM). All SDRAM was compatible with each other, just the speeds changed. So you can use your old slow DIMMs as long as you don't mind that slowing down all your memory accesses.
Finally, the reason RDRAM failed isn't as simple as your comments that the RAM people screwed RAMBUS. The problem was the RAM people didn't feel like being screwed by RAMBUS. RAMBUS wanted license fees on all RAM made (see their grab at applying their patents to DDR) and so they tried to make RDRAM the standard. Intel also wanted more money per motherboard sold (not just happy selling the CPU). Intel's first attempt at making this happen was Slot 1, where they force-bundled the 2nd level cache memory in with the CPU (2nd level cache SRAM revenue could be $30-$50 per mobo back in the Socket 7 days). Note that 2nd level cache moved to the main CPU chip later. Intel additionally decided to license slot 1, claiming patents on it. Regular front side busses could not be patented, as they were purely functional, considered the most basic way to do something. Slot 1 was positioned so as to patent the physical connector and form factor so they could enforce their fees.
Intel decided to threaten VIA (a very popular Socket 7
http://lkml.org/lkml/2005/8/20/95