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Quad PCIe Motherboard
SlipKid writes "PCI Express Graphics cards have allowed for some new and innovative ways to increase rendering horsepower in Desktops and Workstations. Recent introductions of NVIDIA's SLI and ATI's CrossFire technology have enabled dual PCIe Graphics cards in a
load-sharing architecture. Motherboard manufacturers are jumping into the fray now and Gigabyte has released a Quad PCI Express graphics enabled motherboard, capable of running four cards at once. The board is not capable of running Quad SLI, mostly due to lack of NVIDIA driver support currently but it does offer support for eight simultaneous display outputs on four Graphics cards."
I would love to see a quad-Opteron mobo with four x16 PCIe slots but arranged in a way that traffic is spread across all HT links. So that I could use it to put 4 PCIe SATA cards, and have the highest possible read/write I/O throughput for a Linux software RAID array. Hardware RAID is out of the question, since no constructor offers a way to create arrays of disks across 3 or more cards. An Opteron has 3 HT links, 2 of them could be used as coherent links to other CPU's, and 1 of them could be used as a link to an external PCIe bridge chipset. The solution I would like to see implemented is one where 4 PCIe bridge chipsets would be connected to their own Opteron, via their own HT link. And each PCIe bridge chipset could provide at least one 16x slot.
Some numbers: each of the four x16 PCIe bus would allow for 2500 MT/s * 16 bits / 8 = 5000 MB/s of traffic in each direction. And each of the 4 HT links: 1600 MT/s * 16 bits / 8 = 3200 MB/s. The global amount of I/O would be 3200 MB/s * 4 = 12.8 GB/s in each direction ! (HT links are the bottleneck). To resolve this bottleneck AMD would either need to increase their width from 16x16 to 32x32 bits or need to increase the signal freq from 800 MHz to 1.25 GHz (current limit is 1 GHz for coherent links and 800 MHz for the ones facing outside worlds -- chipsets seem to lag a little bit regarding HT frequency).
But for some reason no constructor has ever designed such a board (Tyan only did it with 2 PCIe chipsets on their S2895 mobo). Why oh why is that the case ?! Seems like nobody understands the true potential of HT. This could provide a low-cost solution to so many perf issues I have seen in the various companies I have worked for... Argh !
3DFX SLI = Scan Line Interleaving
Nvidia SLI = Scalable Link Interface
Yes, Nvidia based their version on the ideas they acquired from 3DFX when they bought them out, but the actual techniques they use now are much more advanced. IIRC, the driver does automatic load-balancing, in the sense that if there are more polygons on one section of the screen than another, the rendering will be split so that each card still renders approximately half of them - even if that means one card is doing 75% of the actual screen resolution.