Intel Ships Core Duo-based Xeon

diegocgteleline.es writes "According to The Register, Intel has begun shipping a power-efficient dual-core "Xeon LV" and claims that it consumes no more than 31 W running at 2 Ghz, with a 667 Mhz frontside bus and sharing 2 MB of L2 between the two cores. The new chip has "four times the performance-per-Watt of its existing 2.8GHz LV Xeon CPU", not surprising given how slow and power inefficient those CPUs were. While this looks like a move to make AMD shares continue yesterday's tendency, it looks like Intel is starting to catching up?"

Comments

Sorry Intel

[9mm Censor]

Opterons set the bar at 64bit processors for server chips.

Re:What's new?

[tomstdenis]

Just a correction, if I'm not mistaken that's 2MB of L2 ... period. Not "per core". That means internally the bus between the cores and the cache is shared. Chances are there is some facilities to "prefer" a region of the cache [e.g. dual-ported] but as far as I've seen logically it's a 2MB cache both cores can access.

Tom

Dual processor configurations

[NekoXP]

Xeon LV supports SMP.. I think that is the only difference.

Now it's been released I wonder if Apple are going to put out a PowerMac based on it..

Re:Dual processor configurations

[Jeff DeMaagd]

I wouldn't expect it to be PowerMac material. Code name Woodcrest is a better fit. It seems to clock a lot better (up to 3GHz, with a decent CPI to boot) with better cache (4MB per chip) and a better front side bus, up to 1333 MHz and support 64 bit instructions.

Re:What's new?

[jdb8167]

Two things, SMP and a 34-bit address bus for up to 16GB of RAM.

No words needed.

[Anonymous Coward]

Dual Dual-Core Opterons vs Xeon (Paxville)

Re:Power efficiency is all good and nice but...

[JollyFinn]

While it might be "cripled" by FSB.
Its faster than fastest opteron on perl and circuit layout part of spec int. And looses badly on chess ;)
In overall its EQUAL to fastest dual core opteron on spec int.

The fact remains that FSB is just ONE variable in huge nets of variables in performance equation.
Using more cache means less memory accesses outside chip, using better prefetcher, helps memory access and soon, the off die memory accesses take such a small fraction of time, on MOST software that ondie memory controller vs FSB becomes non issue. [The percentage of improvement from ondie becomes less important than being flexible at new memory technologies on old sockets.]

And memory accesses only take part of the time that must be improved other part is improving core, which part is often more important than improving the offchip memory accesses when there is enough cache. [depends on code].

Take one thing that competitor can potentially do some what faster means nothing if you separate it from all the other aspects of CPU.