Micro-Pump is Cool Idea for Future Computer Chips

core plexus writes to tell us that Engineers at Purdue University have designed a tiny 'micro-pump' cooling device that can be used to circulate coolant through the channels etched on an individual chip. From the article: "The prototype chip contains numerous water-filled micro-channels, grooves about 100 microns wide, or about the width of a human hair. The channels are covered with a series of hundreds of electrodes, electronic devices that receive varying voltage pulses in such a way that a traveling electric field is created in each channel. The traveling field creates ions, or electrically charged atoms and molecules, which are dragged along by the moving field."

Comments

Cooling is not the only problem

[thpr]

Yes, 3D is a neat application, but cooling is not the only challenge in 3D semiconductor electronics. Another perspective on 3D is available in Business Week's More life for Moore's Law article.

For example, one of the assumptions that exists on a semiconductor wafer before it is printed is that it is effectively flat (a typical peak to valley range on a modern wafer within the expected field of a chip is on the order of 175 to 200 nm)

Polishing to that accuracy once structures have been placed on a semiconductor wafer is difficult. Getting a consistent layer of material when you are polishing an uneven surface (uneven due to vias [connections] to the other layers of silicon present) is downright challenging. Another problem with printing transistors on anything but a pure wafer is the issue of reflection. Thin layers of materials on a semiconductor are semi-transparent and not perfectly vertical. Those angled and curved structures produce reflections. Those reflections can cause problems in printing later layers (because of constructive and destructive interference of the light used to expose the photoresist). Those reflections mean that modeling the exposore process of a 3D semiconductor is a VERY challenging task.

Such items are not of concern today, because the later structures placed on the wafer are generally metal lines or capacitors for DRAMs or lenses for image sensors, etc. These are all large and some level of imprecision is acceptable. While variation can cause differnet RC characteristics in metal lines, the timing models in the library or other models can account for this variation. In fact, Matrix Semiconductor has been producing 3D DRAM since about 2004, which shows that heat isn't necessarily the problem, and DRAMs (and memory in general) are a reasonable application for 3D technologies (likely because the capacitors are generally large in relative terms).

Transistors, however, are much more sensitive to variation, and the variation in later polishing used today is too rough for the effective printing of transistors. While I don't doubt that there are situations where the density will be valuable, I think 3D processors and custom chips (in consumer electronics, et al.) are as much an economic issue as a cooling/technical one. (in other words, with my understanding of current roadmaps, you will decrease semiconductor yield to such a degree that 3D may not be economically viable, even if the cooling problem is solved.)