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A Greener Chip Manufacturing Process
gardenermike writes "A new chip manufacturing process has been developed which uses UV light instead of high temperatures to prepare the silicon. This could lead to cheaper chips and greener factories if it pans out. Apparently the main problem is defects in the material, which are currently 'ironed out' as a side-effect of the extreme temperatures used."
as the defect ratio issue would be negated by the size of the technology being produced.
:)
for custom fabricating nanocircuitry for nanomachines this seems like an awesome idea.
so how long till we have a swarm of replicators based on this technology
https://www.gnu.org/philosophy/free-sw.html
Man guys, these chip jokes REALLY suck. This isn't a joke. They're horrible. Try harder.
I'd hardly call it a side-effect to have a process that minimizes defects. I'd rather call that an essential-effect.
"It's the height of ridiculousness to say for those 9 lines you get hundreds of millions."
Not so fast.
SiO2 will still be used in non-critical layers and in less-than-leading-edge technology, which there is a lot of, and will be for a long time to come. Not all chips are CPUs. In fact, most aren't. It's worth a look.
TFA also said it might allow manufacturing semiconductors on substrates (other than Si) which heretofore wouldn't be possible due to their inability to withstand the high temperatures.
...the future crusty old bastards are already drinking the Kool-Aid.
Appart from the fact that it might be replace by High K/Low K (whatever that may be), saying:
"could reduce the prices of electronic devices for consumers and, of course, create a positive environmental impact"
Seems wrong: Isn't production only a small part of actual environmental impact?
Of course any "greener" pruduction method helps, but when I think about green chips, I think about chips like the efficeon chip from Transmeta.
Not only that, but there are a lot of harsh chemicals that are used in manufacturing semiconductors, and this is a concern on many levels (exposure by humans, contamination of things such as water supplies, etc.). When I saw "greener" chip manufacturing process, I was initially thinking and hoping that this was what they were referring to, but lower power usage is obviously a nice benefit as well.
Firstly, I have to say that, what they claim to serve as a >novel> technique is not completely novel. Of course, it was known that SiO2 could be formed by other means then sintering ( heating the silicon and letting the oxygen atoms dissolve in silicon ) but the problem has always been the purity.
Semiconductors, especially devices in nanometer scaling need to be extremely pure. Their lattice structure -hence their electrical effects- can easily be distorted or failed by very little deviations, say, in dopant concentrations random dopant fluctuations. This is shortly called , RDF.
RDF has become a major concern especially for the newcoming generations because basically when you scale down the channel length, the channel lengths are becoming so narrow (and small) that only about 100 hundred dopant atoms fall inside the channel volume. This , obviously, increases the sensitivity and failure rate of these transistors, let alone their variations (like threshold voltages) in a single die.
From a mass production point of view, we want to get as uniform parameters as we can from a complete die. The ratio of successful ( uniform and working ) transistors to the total die area divided by a single transistor area ( which means the total number of transistors we wanted to harvest from that die ) gives us the `yield`.
Now, taking into account the fact that even a failure of a single transistor, could lead to the failure of an entire word line of an SRAM , the yield strongly influences the SRAM or chip reliability.
And for the companies, it does not matter whether you prepare the chip at room temperature but in a more sloppy way, because ultimately it is going to cost more !
Of course the need for extreme purity in nanoscale devices is not realized completely. The reason is that we have not produced those chips yet. However, these issues ( especially RDF and process variations- you can google these and see yourself) are very hot topics in LOW POWER VLSI design.
The people who work in these fields are surely aware of the need for an accurate fabrication and will just ignore this kind of work. There are some papers that try to reduce these effects only to succeed in a relatively low way.
In modern research, you can easily publish a paper by changing the slightest detail of a published paper or you can slightly vary this known application and claim that you have come up with a totally novel ida.
This is a draw-back.
In short, they are not going to make anything green, UNLESS of course, they find a better and reliable method satisfying the needs of the upcoming nanoscale devices.
Then I would shut up
There's plenty of room at the bottom! Richard P. Feynmann