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Rambus in Violation of Monopoly Laws
surfingmarmot writes to tell us that in a recent ruling the Federal Trade Commission declared that Rambus had unlawfully monopolized four computer memory technology markets. From the article: "In an opinion by Commissioner Pamela Jones Harbour, the Commission found that, through a course of deceptive conduct, Rambus was able to distort a critical standard-setting process and engage in an anticompetitive 'hold up' of the computer memory industry. The Commission held that Rambus's acts of deception constituted exclusionary conduct under Section 2 of the Sherman Act and contributed significantly to Rambus's acquisition of monopoly power in the four relevant markets. The Commission has ordered additional briefings to determine the appropriate remedy for 'the substantial competitive harm that Rambus's course of deceptive conduct has inflicted.'"
FINALLY has come around.
This could be the knife to the heart for RAMBUS, as I'm fairly certain a number of DRAM makers are going to be lining up to take shots at them.
Think "Hysterical Passenger" from Airplane!.
Chas - The one, the only.
THANK GOD!!!
The Slashdot front page is filled with crimes holding up progress in the field of computing.
- Vista tries to pretty up the PC case to shove DRM down our throats, by requiring the purchase of new DRM ready hardware like PVP screens.
- Rambus conspired to muddy the RAM providing market, so motherboards are made obsolete sooner rather than later, since we have to settle on one RAM standard to upgrade. If we don't have it, then we have to change the whole motherboard and probably CPU too. If it's in a mass produced computer, the consumer has to pitch the computer to upgrade.
- Apple's DRM found to be hindering customer use of media.
I wish we'd stop letting companies plan to build in failure mechanisms in their product. I'd pay 20% more for a computer that I knew would have new parts available in 5 years when it starts to legitimately wear out. That extra money could go to the collection of old computers and reusing or recylcing the materials in them in an ecologically sound way.
Oh You POS
The FTC doesn't have that kind of power. Here's what they can do:
15 U.S.C. 45(b). The FTC said what Rambus' unfair acts were. FTFA: "Rambus withheld information that would have been highly material to the standard-setting process within JEDEC." "JEDEC members acted reasonably when they relied on Rambus's actions and omissions and adopted the SDRAM and DDR SDRAM standards." "Rambus was able to conceal its patents and patent applications until after the standards were adopted and the market was locked in."
According to the text of the statute, the FTC can order Rambus not to hide their patents any more. That's a pretty hollow victory.
On the other hand, this ruling shows that Rambus violated antitrust law. That means anyone sued by Rambus for patent infringement has a strong patent misuse defense, which should get the case dismissed almost immediately. Head down to your local law school library and look up: Donald S. Chisum, Chisum on Patents 19.04 (2006). Basically, the upshot is that Rambus won't have its patents thrown out (other people besides JEDEC members could be infringing while not implementing the specification), but at least as regards those implementing the JEDEC spec, the patents will be unenforceable.
This post expresses my opinion, not that of my employer. And yes, IAAL.
One of the markets in "Intellectual Property" in which it claims to hold monopoly power due to rightfully issued patents is "clocking technology", specifically for synchronous DRAM busses. Before the Chief Administrative Law Judge appointed by the FTC they made argument of their specific ownership of "source synchronous clocking technologies".
Does Rambus have any valid patents on source synchronous clocking methods, systems or devices to accomplish that practice?
I also know what clocking method is employed in Rambus' commercial RDRAMS. Does Rambus have any patents on that?
Here's what Rambus has patents on:
"FIG. 8b illustrates how each device 51, 52 receives each of the two bus clock signals at a different time (because of is propagation delay along the wires), with constant midpoint in time between the two bus clocks along the bus. At each device 51, 52, the rising edge 55 of Clock153 is followed by the rising edge 56 of Clock254. Similarly, the falling edge 57 of Clock153 is followed by the falling edge 58 of Clock254. This waveform relationship is observed at all other devices along the bus. Devices which are closer to the clock generator have a greater separation between Clock1 and Clock2 relative to devices farther from the generator because of the longer time required for each clock pulse to traverse the bus and return along line 54, but the midpoint in time 59, 60 between corresponding rising or falling edges in fixed because, for any given device, the length of each clock line between the far end of the bus and that device is equal. Each device must sample the two bus clocks and generate its own internal device clock at the midpoint of the two."
Ok, so the Rambus devices that are patented generate clocks that are aligned in phase with each other along the extent of the bus.
A source synchronous clocking system would have clocks that vary in phase along a bus in a fashion nearly equal to the phase variation of the data that are transmitted with the clock.
Here's what H&F patented:
"In the preferred embodiment, two sets of these delay lines are used, one to generate the true value of the internal device clock 73, and the other to generate the complement 74 without adding any inverter delay. The dual circuit allows generation of truly complementary clocks, with extremely small skew. The complement internal device clock is used to clock the `even` input receivers to sample at time 127, while the true internal device clock is used to clock the `odd` input receivers to sample at time 125. The true and complement internal device clocks are also used to select which data is driven to the output drivers. The gate delay between the internal device clock and output circuits driving the bus in slightly greater than the corresponding delay for the input circuits, which means that the new data always will be driven on the bus slightly after the old data has been sampled."
So they use the SAME clock to operate both the input samplers and output drivers in the system they "invented" in 1990 and that everybody and their cat infringes on? Or do you claim otherwise? Did they claim otherwise before the USPTO and in Federal District court?
Interesting.....
"One important part of the input/output circuitry generates an internal device clock based on early and late bus clocks. Controlling clock skew (the difference in clock timing between devices) is important in a system running with 2 ns cycles, thus the internal device clock is generated so the input sampler and the output driver operate as close in time as possible to midway between the two bus clocks."
So "clock skew" is the difference in clock timing between devices? Hummm. They're not suggesting that clocks have no skew from device to device along their Rambus, are they? But that's stupid, because the data that they're trying to latch with their "input samplers" does have timing skew from device to device"
A source synchronous clocking scheme would have a timing skew due to time of
Processor = $114
Mobo = $82.99 + $6.13 S&H
Video card = $155.99 + $5.64 S&H
600 watt power supply = $69.99 + $8.02 S&H
case = $64.99 + $16.21 S&H
20 gig hard drive = $79.99
2x1 gig memory? Here.
This isn't even a top-of-the-line system, but good (i.e., best customer-rated) memory is going to cost more than anything else. The cheapest on that page that is rated 5 out of 5 is $174.99, not including shipping.
I dream of a better world... one in which chickens can cross roads without their motives being questioned.