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AMD Announces Quad Core Tape-Out
Gr8Apes writes "The DailyTech has a snippet wherein AMD announced that quad core Opterons are taped out and will be socket compatible with the current DDR2 Opterons. In fact, all AM3 chips will be socket compatible with AM2 motherboards. For a little historical perspective, AMD's dual-core Opteron was taped out in June 2004, and then officially introduced in late April, 2005.' AMD also claims that the new quad processors will be demo'd this year. Perhaps Core 2 will have a very short reign at the top?" From the article: "The company's press release claims 'AMD plans to deliver to customers in mid-2007 native Quad-Core AMD Opteron processors that incorporate four processor cores on a single die of silicon.'"
I am glad to see AMD making progress on its quad core chip. No longer can megahertz bring mega bucks. Moore's law doesn't mean Moore money. (Ok, I'll stop now.) We have seen more chip innovation over that past 4 years than I thought was possible.
In case you are wondering what the differences are between AMD and Intel in quad core designs, this comes from TFA:"Intel has recently accelerated its quad-core plans; the company recently announced that quad-core desktop and server chips will be available this year. Intel's initial quad-core designs are significantly different than AMD's approach. The quad-core Intel Kentsfield processor is essentially two Conroe dice attached to the same package. AMD's native quad-core, on the other hand, incorporates all four cores onto the same die."
I cannot wait for comparative benchmarks. I wonder how much ground Intel will gain by being first to market.
Information wants a fueled airplane waiting at the hangar and no one gets hurt.
Way back in the 1960's the way you designed a printed circuit board, or an integrated circuit, was to get a big piece of clear plastic and lay out the lines with red tape. They used red tape so you could see through it, in order to align the tape exactly over the layer below ( most PC boards use at least two layers, IC's at least 5 layers.) As you can imagine, a rather tedious, error-prone process.
When you were done with the tape and exacto knifes, you'd hand the plastic over to the foundry guys, who would photographically reduce each layer to the appropriate microscopic masks.
Sometime in the mid 70's, computers and optical printers got cheap and good enough so you could actually design the lines and layers on a COMPUTER SCREEN. Sales of red tape went way down. Nobody missed the red-tape days.
Nowdays just about everything is computerized in this process. THere's never a plastic sheet or tape or paper stage-- the bit images go directly form the design mprogram to the foundry.
But they still say "The design got "taped out"."
The next step after using mylar and rubylith was using CAD, and sending a nine-track magnetic tape of the data to the foundry. So "tapeout" came to mean writing the final magnetic tape.
Nowdays, of course, the data is usually transferred over the internet, so no tape of any kind is involved (not even duct tape). But it is still called tapeout for historical reasons.
Tapeout, a.k.a. RIT (Release-In-Tape) is just an old term, similiar to RTM (Release to Manufacturing), which is becoming obselete for software. It seems that semiconductor design terminology has a much longer life than the chips-- we still call design rule checking programs, "DRC decks." Why a "deck?" Remember punch cards? Speaking of cards, that's a netlist.
My favorite's "kerf," the area between chips on a wafer that is lost when they're diced. The term was borrowed from sawmills.
Who do you get to be an expert to tell you something's not obvious? The least insightful person you can find? -J Roberts
i think the answer is- because they can.
u bberDuckies.html
here is a very interesting article on the subject of product pricing.
http://www.joelonsoftware.com/articles/CamelsandR
------ hi mom
Inside the linked stories, they mention how Deerfield (the 65nm process chips) have dropped from the roadmap. They extrapolate that to mean that these will be the only 65nm chips.
Another decrease in power consumption can be obtained by lowering voltages, which I understood from another article to be handled on K8L by introduction of another new tech - but I don't have that link at the moment.
And lastly, it's not just pure power consumption you're worried about these days, but power consumption per computational unit. What do I care if a 4 way processor consumes twice as much power as a 2 way processor, if it can do 8 times the work? That's still a halving of power consumption in my book.
The cesspool just got a check and balance.
IBM has had Quad Cores since 2005. They are working on many more cores in their Power6 / Power7 lines;
http://en.wikipedia.org/wiki/POWER5
IBM has often charged per the CPW, or processing power and group level, for their software. They license the processor cores. You can have a box with 4 processors and be licensed for 3. If you want to use the 4th in the box, you pay an upgrade fee.
Interesting stuff.
They won't care until one performes significantly better than the other.
Conversely, it's rash of you to make TBBA's. (That's Truth by Blatant Assertion). Let me show you how that works, prior to Core 2 - It's rash of you to say the new CPU with 2 Intel cores will beat 2 AMD cores, since even a single AMD core already trounces the Pentium Dual Core CPU.
It completely ignores all relevant facts. The new AMD cores will most likely be 65nm, putting them on the same footing as Intel's new chips. The AMD quad to Intel quad can be closely compared to the previous Intel Pentium "Dual Core" - 2 slapped together cores - vs AMD's dual core on a single die. Many of the same dynamics exist, with one major difference - AMD is doing with the quad what Intel did with the Core 2 - the AMD quad is sharing 4MB of L3 cache. That's one more level than Intel's offering, btw. Intel's quad will be 2 Core 2's slapped together, sharing a single FSB. AMD doesn't have a FSB bottleneck. Anandtech's review of the Core 2 comes up just short of stating that the FSB is going to bottleneck Intel's 2P system (Woodcrest) probably, and wisely, waiting until 2P benchmarks come in. We're all waiting on those, as they will reveal much.
In any case, I am speculating and stated as much as I backed my speculation with what information has been released to date. You are free to draw your conclusions however you'd like, but do so with some basis on known facts.
The cesspool just got a check and balance.
What I'd really like is asymetric cores... something like a really power efficient simple 1Mhz core, but when needed, a more powerful 2Mhz core steps in... then a 4Mhz core, then 8Mhz core... The box can have like 32 cores, each one 2x as fast as the last... (oh, I wish!) while 99.9% of the time, you're only using the simple 1Mhz one (ie: how much cpu power does it really take to update the clock?).
(it doesn't have to start at 1Mhz... it could start at 100Mhz, jump to 500Mhz 2nd core... 1Ghz 3rd core... and 2Ghz 4th core---so an idle CPU would use very little power).
Besides, most of the time, you won't use the cores equally anyway. You'll likely run 1 "heavy" app (some game), and a few very light ones.
"If anything can go wrong, it will." - Murphy
Research about what? The fact that AMD designed the Hammer core to use a switching memory interface instead of a bus interface? The fact that Intel's initial one-bus-tap-per-core system makes it difficult to keep bus speeds high? Not to mention I haven't found documentation that Intel has moved away from their multi-tap approach.
There's also the fact that most consumer computational loads don't yet scale across multiple cores. Sure, you might have applications that spawn ungodly numbers of threads, but that doesn't mean many of those threads are doing an appreciable amount of work. If you have a decent task scheduler in your OS, one fast core is still Good Enough.
AMD went beyond Intel with the K7. That core lineage performed more data per-clock that Intel's competing Prescott-based cores. Now Intel is working to outperform AMD's K8, while AMD seems only to be focusing on adding more cores.
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Was this nugget of insight any less valid reguarding the now defunct 939 slot, or the soon to be released AM3 slot?
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Open Source Sysadmin
Most of the datacenters around here lease gear, and the normal span is 3 years. So every three years you replace the gear. We have some crusty/musty things on our datacenter floor that were purchased, and because of that we now have to ebay parts for 10 year old DEC VMS boxes. The cost to maintain equipment after the third year goes up significantly, often support contracts from vendors skyrocket to where it doesn't make business sense to continue using that old gear anymore.