AMD Announces Quad Core Tape-Out
Gr8Apes writes "The DailyTech has a snippet wherein AMD announced that quad core Opterons are taped out and will be socket compatible with the current DDR2 Opterons. In fact, all AM3 chips will be socket compatible with AM2 motherboards. For a little historical perspective, AMD's dual-core Opteron was taped out in June 2004, and then officially introduced in late April, 2005.' AMD also claims that the new quad processors will be demo'd this year. Perhaps Core 2 will have a very short reign at the top?" From the article: "The company's press release claims 'AMD plans to deliver to customers in mid-2007 native Quad-Core AMD Opteron processors that incorporate four processor cores on a single die of silicon.'"
I am glad to see AMD making progress on its quad core chip. No longer can megahertz bring mega bucks. Moore's law doesn't mean Moore money. (Ok, I'll stop now.) We have seen more chip innovation over that past 4 years than I thought was possible.
In case you are wondering what the differences are between AMD and Intel in quad core designs, this comes from TFA:"Intel has recently accelerated its quad-core plans; the company recently announced that quad-core desktop and server chips will be available this year. Intel's initial quad-core designs are significantly different than AMD's approach. The quad-core Intel Kentsfield processor is essentially two Conroe dice attached to the same package. AMD's native quad-core, on the other hand, incorporates all four cores onto the same die."
I cannot wait for comparative benchmarks. I wonder how much ground Intel will gain by being first to market.
Information wants a fueled airplane waiting at the hangar and no one gets hurt.
Way back in the 1960's the way you designed a printed circuit board, or an integrated circuit, was to get a big piece of clear plastic and lay out the lines with red tape. They used red tape so you could see through it, in order to align the tape exactly over the layer below ( most PC boards use at least two layers, IC's at least 5 layers.) As you can imagine, a rather tedious, error-prone process.
When you were done with the tape and exacto knifes, you'd hand the plastic over to the foundry guys, who would photographically reduce each layer to the appropriate microscopic masks.
Sometime in the mid 70's, computers and optical printers got cheap and good enough so you could actually design the lines and layers on a COMPUTER SCREEN. Sales of red tape went way down. Nobody missed the red-tape days.
Nowdays just about everything is computerized in this process. THere's never a plastic sheet or tape or paper stage-- the bit images go directly form the design mprogram to the foundry.
But they still say "The design got "taped out"."
The next step after using mylar and rubylith was using CAD, and sending a nine-track magnetic tape of the data to the foundry. So "tapeout" came to mean writing the final magnetic tape.
Nowdays, of course, the data is usually transferred over the internet, so no tape of any kind is involved (not even duct tape). But it is still called tapeout for historical reasons.
Tapeout, a.k.a. RIT (Release-In-Tape) is just an old term, similiar to RTM (Release to Manufacturing), which is becoming obselete for software. It seems that semiconductor design terminology has a much longer life than the chips-- we still call design rule checking programs, "DRC decks." Why a "deck?" Remember punch cards? Speaking of cards, that's a netlist.
My favorite's "kerf," the area between chips on a wafer that is lost when they're diced. The term was borrowed from sawmills.
Who do you get to be an expert to tell you something's not obvious? The least insightful person you can find? -J Roberts
i think the answer is- because they can.
u bberDuckies.html
here is a very interesting article on the subject of product pricing.
http://www.joelonsoftware.com/articles/CamelsandR
------ hi mom
Research about what? The fact that AMD designed the Hammer core to use a switching memory interface instead of a bus interface? The fact that Intel's initial one-bus-tap-per-core system makes it difficult to keep bus speeds high? Not to mention I haven't found documentation that Intel has moved away from their multi-tap approach.
There's also the fact that most consumer computational loads don't yet scale across multiple cores. Sure, you might have applications that spawn ungodly numbers of threads, but that doesn't mean many of those threads are doing an appreciable amount of work. If you have a decent task scheduler in your OS, one fast core is still Good Enough.
AMD went beyond Intel with the K7. That core lineage performed more data per-clock that Intel's competing Prescott-based cores. Now Intel is working to outperform AMD's K8, while AMD seems only to be focusing on adding more cores.
tasks(723) drafts(105) languages(484) examples(29106)