China to Make $125 PCs

TechFreep writes "A Chinese computer company hopes to sell low-cost PCs to schools and government agencies, but allegations of ripped-off processor designs might slow the effort. From the article: 'Chinese-based ZhongKe Menglan Electronics Technology Co. will produce several thousand low-cost PCs to distribute to schools and local governments. The PCs, which will initially sell for $150 to $175, will run on Linux and include 256Mb of RAM, a 40 or 60GB hard drive, and a Godson-2 CPU clocked between 800Mhz and 1Ghz. If initial sales of the product are successful ZhongKe will begin mass production of the units for sale at around 125 US dollars. However, the Godson-2 CPU included in the PCs has come under scrutiny of late. BLX IC Design Corp., producer of the Godson-2, produced its first working prototype in 2005. The chip clocked at 500Mhz, and BLX at the time claimed the Godson's performance rivaled that of higher-clocked Pentium III CPUs. However, the chip's architecture has gotten attention around the industry for its similarities to the MIPS chip from MIPS Technologies Inc. According to market research group In-Stat, the Godson-2 is about 95 percent compatible with the MIPS R10000, which was introduced in 1995.'"

Comments

MIPS patents?

[tepples]

Plasma implements the MIPS architecture minuses the patented parts. Could the Godson CPU be a variant of this?

Re:MIPS patents?

[pchan-]

The MIPS architecture is a popular one with people who implement their own cores. In fact, it is rather common for computer science/engineering students to implement their own using FPGAs, based on the commonly used Computer Architecture by Hennessy and Patterson. The architecture is extremely simple, straightforward, and easy to implement.

I believe you can implemented a near complete MIPS R3000 core with only minor differences and avoid any patent issues (as long as you don't call it a MIPS). Some of the ops on the newer cores are still encumbered and cannot be implemented without paying money to MIPS Technologies. I've worked with a couple of MIPS clones, some by American companies, and there is nothing illegal about them. In fact, it would be far more surprising if the Chinese companies wasted the time creating their own architecture instead of basing it on a proven one.

Re:MIPS patents?

[PAPPP]

It's worth noting that the patent most likely to be stepped on in dealing with MIPS is US patent 4,814,976, which covers the unaligned load/store instructions lwl, lwr, swl and swr. This patent expires 2006-12-26, which won't be long now. Google for "Lexra" "MIPS" and "Patent" for details of the various spats over the patent.
Apparently some of the more recent extensions fall under other patents, but the basic archetecture will be entirely unencumbered after this one expires. And as a Computer Enginering student I can tell you as ISAs go it's far and away the easiest useful one to impliment.

Re:MIPS patents?

[pchan-]

But you may be one of the fortunates who go to school where Hennessy is president, so you may have learned MIPS there =P

I take it you mean Stanford. I went to UCLA, but many people I've met from different schools in the US have used the same architecture book. I'm talking about computer architecture, not just assembly language. The complexity of the x86 processors is far too great to teach them to undergrads. However, in about a hundred hours of work, one lab partner and I were able to construct a working MIPS-architecture CPU (on a Xilinx FPGA) starting with nothing but gates, flipflops, and other basic elements.

Now, since you know x86 assembly, let me teach you MIPS assembly in one minute:
32 registers, r0-r31. r0 is hardcoded to zero. jal/bal (jump/branch and link) push the PC to r31. otherwise, all registers are equal.

li rD VAL ; load to register rD (destination) immediate value VAL
lw rD rS ; load word at address stored in rS (source) to
add/sub/... rD rA rB ; perform op on registers A and B, store to register D
sw rD rS ; store word at rD to address in rS

You'll be doing a lot of load/stores. The instruction after a branch statement gets executed even if the branch is called. The rest is just details (extend to half-words and bytes at your convenience). There are no index registers, no flags, no predicates, nothing. Congratulations, you are now qualified to program a MIPS processor.

Re:MIPS patents?

[Jamie Lokier]

No, often you can find an instruction to put after the branch. Sparc is the same. It's called the "branch delay slot", and it's a way of reducing the pipeline flush penalty.

So what are we upset about?

[BadAnalogyGuy]

Are we upset that some defunct chip designer isn't getting their cut? Or is it that the Chinese are making cheap computers for themselves instead of for us? Or maybe it's that the Chinese aren't outsourcing their production to the West?

I don't know what's the problem here. It sounds like a great idea to put as many people on the internet as cheaply as possible because more people means more information and more information transfer. Now Wang Chung in the sticks can be just as up to date with government propaganda as Chung King in Shanghai is.

Bruce Lee unavailable for comment.

American retailers not much more

[davidwr]

I've seen several "house brand" PCs from major retailers that ran under $250 with Windows and under $150 without when on "we do this almost every week" sales. Yes I know what "loss leader" means but at these prices the Linux boxes probably wholesale for $150-$175. Large school systems and other institutions would probably pay very close to wholesale.

Re:Why is this so hard?

[grumbel]

Such computers seemed to handle word processing, web browsing, email, etc.

Not when you want to use OpenOffice and Firefox. I am not sure if they really want to, but todays applications simply require quite a bit more CPU and RAM then yesterdays applications, even for the very same jobs. So unless they also write the low-spec software, they better make sure that they have enough power to run current days applications.

Chinese attitude towards Linux

[patio11]

"We were going to pirate it, but couldn't figure out how."

Re:95% compatibility?

[shadow_slicer]

'Instriial espionnage' is not needed. The MIPS instruction set and architecture are standard reading for anybody in the field. They're not saying they copied the layout or instruction set, it's more like the API.

All processors have a language they understand, a sequence of bits that have an arbitrary meaning to them. And these are usually published far and wide, so that people can write compilers and operating systems and assemblers for this processor. MIPS in particular is very popular to study because the simple structure makes it possible for teachers to make creating a VHDL or Verilog implementation of a simplified MIPS instruction set into a half-semester project.
In fact I doubt their implementation is anywhere near the same caliber as the Pentium III implementation, even if they claim the same speed. What probably happened is they have access to more modern, smaller fabrication methods so they can cram more transistors into the pipeline. And even soft IP cores in FPGAs can hit 200MHz, so a well designed core could probably hit 500 MHz in an ASIC.

That being said, creating a full super-scalar CPU implementing even 95% of the MIPS 64-4 version of the instruction set in silicon is difficult. I was not familiar with this specification, but a quick search on google reveals that

The Mips R10000 is a dynamic superscalar microprocessor that implements the 64-bit Mips-4 Instruction Set Architecture. It fetches and decodes four instructions per cycle and dynamically issues them to five fully pipelined low-latency execution units. Instructions can be fetched and executed speculatively beyond branches. Instructions graduate in order upon completion. Although instructions execute out of order, the processor still provides sequential memory consistency and precise exception handling.The R10000 is designed for high performance, even in large real-world applications which have poor memory locality. With speculative execution, it calculates memory addresses and initiates cache refills early. Its hierarchical nonblocking memory system helps hide memory latency with two levels of set-associative, write-back caches.

This is a really beefy processor that was probably state of the art in its time. Of course that was over 10 years agos. Is it really so suprising China is only 10 years behind in chip design? After all aren't most of the chip fabrication facilities in east Asia? I'd imagine there would be quite a few people who after a few years decide they want to be on the other end of the process.