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AMD Unveils Barcelona Quad-Core Details
mikemuch writes, "At today's Microprocessor Forum, Intel's Ben Sander laid out architecture details of the number-two CPU maker's upcoming quad-core Opterons. The processors will feature sped-up floating-point operations, improvements to IPC, more memory bandwidth, and improved power management. In his analysis on ExtremeTech, Loyd Case considers that the shift isn't as major as Intel's move from NetBurst to Core 2, but AMD claims that its quad core is true quad core, while Intel's is two dual-cores grafted together."
"The two cores fight each other over a very slow external bus, and this creates a performance bottleneck."
Sorry, but nothing in your argument supports the claim that the design includes a "very slow external bus". Yes, the bus is not faster like you'd like it to be. Yes, it may ultimately be a bottleneck in performance. No, it's not a very slow bus.
"When all four cores are on a single peice of Si, all sharing a L3 cache, the chips don't need to fight over the external bus as much."
No. The effectiveness of the caches ultimately are determined by a variety of factors. It is incorrent to assume that cache design in a single die processor is inherently superior.
"Also, true QC chip presents one load to the outside bus. This means that the bus speed does not need to drop because of electrical load."
But it doesn't inherently increase either. Both Intel's and AMD's designs share a single memory controller and ultimately the performance of the system will be effected by how fast the memory and cache system is. Single die versus dual die doesn't have that great an impact.
"There are many people who don't care how the cores are connected as long as the package works."
Ys, and everyone else is crazy.
"The point is that the way the cores are connected have a direct impact on performance."
Right, so let the benchmarks decide. Of course, Intel will have a huge market advantage with their part because AMD will be busy being "true".
"Expect cache thrashing on Intel's true QC chips with heavily threaded loads when it comes out."
So now you're predicting that Intel will suck even after they go to a single die. I guess you've proven that MCM doesn't matter one bit. You just hate anything that comes from Intel.
"How about a fully threaded and loaded database or any other app that will actually stress more than the execution units?"
How about it? Are you claiming that Intel's never seen an application like that? Please be more specific.
It's easy to trash architectures that don't exist with imaginary workloads, isn't it?