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Sony Says Nobody Will Ever Use All the Power of a PS3
Tighthead Prop writes "Sony executive Phil Harrison has made some brash comments about the Cell processor and the PlayStation 3. Harrison says that the current PS3 game lineup is using less than half of the machines power, adding that 'nobody will ever use 100 percent of its capacity.' Is he right? 'The major reason Harrison wants to hype up the "unlimited" potential of the PS3's architecture is to downplay comparisons between games running on Sony's console and Microsoft's Xbox 360. The two systems are not completely dissimilar: they both contain a PowerPC core running at 3.2 GHz, both have similarly-clocked GPUs, and both come with 512 MB of RAM.'"
But Harrison could be correct depending on how he defines 'capacity.' In the world of computer science, one must be careful with the absolute of "never ever" but he hasn't defined capacity sufficiently. Now if he means there will never be a PS3 game capable of using it to the full capacity then he's probably right.
My work here is dung.
Ubisoft says Assassins Creed will have more intelligent AI in the 360 version simply because the three dedicated cores offer more raw horsepower that the PS3 doesn't have. You can also tell that the PS3 has run into some issues regarding the limit of 256MB of texture memory compared to the 360, most textures are all blurry and low res compared to their 360 counterparts. It's the PS2 hype all over again.
Or there is another reason, far less flamebait than my GP post: since the PS3 and the 360 are somehow similar, game developpers will be tempted to build their games on the common ground between those tho systems, therefore, even with a superior PS3, the game will be exactly as it is on the 360.
Not being able to utilize 100% of the computing power is inherent in the design of the Cell processor. Don't get me wrong, its a powerful chip, but its like any multi/distributed/multithreaded-processor. With the Cell it takes time to set up and tear down the configuration between the processors, and if there is no data to work on this very nanosecond then that processor is starved and is essentially spinning and waiting for something to do. The cell has some unique capabilities to configure its processor units in parallel or in a serial data flow through shared memory, but if the task can not be broken down into appropriate computational algorithms that keep every processor unit busy then you are simply not running at 100%.
Having said that, for such a nerd-oriented site, I can't believe some of the parsing going on here, and it must come down at least partially to latent Sony-hate (for whatever reason).
Let's just put the word 'Sony' aside, for ONE second. Just bear with me here.
The PS3's 3.2 GHz Cell processor, developed jointly by Sony, Toshiba and IBM ("STI"), is an implementation to dynamically assign physical processor cores to do different types of work independently. It has a PowerPC-based "Power Processing Element" (PPE) and six accessible 3.2 GHz Synergistic Processing Elements (SPEs), a seventh runs in a special mode and is dedicated to OS security, and an eighth disabled to improve production yields. The PPE, SPE's and other elements ("units") are connected via an Element Interconnect Bus which serves to connect all of the units in a ring-style bus. The PPE has a 512 KiB level 2 cache and one VMX vector unit. Each SPE is a RISC processor with 128 128-bit SIMD GPRs and superscalar functions. Each SPE contains 256 KiB of non-cached memory (local storage, "LS") that is shared by program code and work data. SPEs may access more data in the main memory using DMA. The floating point performance of the whole system (CPU + GPU) is reported to be 2 TFLOPS[74]. PlayStation 3's Cell CPU achieves 204 GFLOPS single precision float and 15 GFLOPS double precision. The PS3 will ship with 256 MiB of Rambus XDR DRAM, clocked at CPU die speed.
That is one deeply weird hunk of hardware. And its pretty fucking cool. Or at least, IBM seems to think so.
Someone has tried to dumb down an explanation like this to our boy Phil and he shat out this 'will never use the full potential' idiocy, which in turn riles all the nerds because its just such a lame thing to say, you can poke holes in it all day (such as, 'why build such a complicated beast if we will never be able to program it - equally idiotic).
So the statement is 100% true, and 100% meaningless.
Like the hamburger truck at the end of my street that claims Greatest Burgers in the Universe.
If Jesus wants me it knows where to find me.
Sure you could use all of the memory fairly easily, but could you soak up every single CPU cycle available to you, especially during the H Blanks? Even if you did that, could you soak up all of the cycles during the (relatively long) V Blank? Remember, even a cycle or two of "slack" would mean you're not using 100% of the machine, and worse, even if you did use up every single cycle of CPU time, you can bet that some marginal machines with slightly marginal processors will roll the screen if you do that.
Even if you managed that, your game would require two joysticks to play and require constant input on both of them, otherwise you'd be wasting a joystick port. I'm not even going to get into the mode switches and whatnot. It's basically impossible to use 100% of any machine like that.
I read the internet for the articles.
The amount of RAM is a different issue from being bottlenecked on the memory subsystem. Long ago a cpu running 1mhz had memory running at the same rate - you could effectively manage a memory access per instruction. Over time CPUs got faster faster than memory got faster. So caches showed up to try to mask it. On a PS2 a cache miss wound up costing 40-60 cycles. Ouch. And the trend has continued, but now it's worse: on the PS3 a cache miss is something ludicrous like 400-600 cycles. Think of it: 500 instructions possible in the time it takes to fetch from memory. Without getting clever, you wind up spending a lot of time stalled waiting for memory. And that's without piles of contention from lots of different threads and processors trying to use the same bus. That's what's meant by being bottlenecked on memory.
IMO, the problem is not the memory latency, it is the CELL-PPE in-order execution the point that kills performance: the CPU instruction pipe becomes blocked waiting for memory load after cache miss. Most modern CPUs that deal with high latency RAMs are usually out-of-order, for increasing IPC, however, the CELL-PPE in-order CPU has to be programmed with explicit prefetch in mind for avoiding pipe stalls. Don't expect great performance from C/C++ code until the compiler gets decent loop unrolling, pipe stall control optimizations, etc. (explicit prefetch will be still necessary for streaming processing).