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First Graphene Transistor
An anonymous reader writes "UK researchers are announcing the first ever workable transistor made of graphene — that's one layer of carbon atoms. It's thinner and smaller than a silicon transistor can ever be, and it works at room temperature. When silicon electronics are dead, this is what many speculate is going to take over. There's slight controversy as they decided to announce their results via a review article, rather than wait for their (submitted) peer review paper to come out."
There are two ways to make graphene I have known, one is to exfoliate graphite and the second one is to produce an oversaturated silicon carbide single crystal, and the graphene will grow epitaxially from the carbon layer on the surface of the silicon carbide crystal. None of these two can be "practical" IMHO. I also believe the researchers claim the new transistor is "practical" just to differentiate them from the old ones. Anyway I will read the real paper on Nature Materials and see what Novoselov's group has done this time.
There is a spark in every single flame bait point.
I mean, the article's about a completely flat sheet of atoms joined in a structure with four edges from eac node. So, why are they showing a ripply surface made from a hexagonal structure, with three edges from each node?
As you note in your follow-up post, the hexagonal bonding structure is correct for graphene. The rippling motion is a result of thermal fluctuations. Normally you don't see it much because the graphene is bonded to a substrate, but as the second link in the main article explains, free standing membranes do actually ripple.
That's true, and actually with current silicon device sizes a single alpha particle strike has the possibility of flipping a bit in an SRAM. This is one part of why NASA uses old cpus -- one of the simplest methods of radiation hardening is to simply use larger structures that require a larger amount of energy to change state. Then they add more shielding and such on top of course.
That's actually not true at all. The chance a transient error (SRAM bit flip) or worse, a long term change in the threshold voltage of a device actually gets worse when the structures are larger. That is because the chance for a radiation event to occur in the gate oxide is linearly proportional to the thickness of the oxide. Fine-line CMOS has thinner oxides, so it is more tolerant.
On top of that, what you are discussing (shielding, structure geometry) is called radiation tolerance, not radiation hardening. A radiation hard IC process implies dielectric isolation between the devices. For example, the use of SOI is quite prevelent in nuclear/space applications. The reason NASA uses old CPUs is because they are available in rad-hard dielectrially isolated technology. Intersil in Palm Bay, FL, still has rad-hard 286s coming off the line right now. Dielectrically isolated IC processes with the feature sizes needed to produce modern CPUs simply do not exist because of the lack of an economic incentive. That is the only reason NASA and DOD use such old CPUs.