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IBM's Snowflake Microchips
Phantom of the Opera writes "The BBC reports that using self-assembled polymers and copying natural patterns, IBM hopes to have microchips that are 30% faster and consume 15% less energy. The secret? Adding a little nothing in all the right places."
So IBM has come up with a manufacturing method using self-assembling molecules to produce regular arrays of 20 nanometer objects on the surface of a silicon wafer with near-perfect yeild. (I presume, since "growth" was involved, it would be possible to use it to construct similarly-spaced objects of sizes within a factor of about 3 to 4 of the size they chose for this process.)
And yesterday we saw a slashdot article referencing work at Rice U, Los Almos Labs, and others, where 5 to 8 nanometer quantum dots on the surface of phovoltaic cells could significantly multiply the efficiency (perhaps into the 60% range) by efficiently creating multiple electron-hole pairs per incoming photon.
Seems to me the two are just ASKING to be combined into an inexpensive manufacturing process for high-efficiency solar panels.
Doubling to quadrupling the output of solar panels while keeping the cost in the current ballpark might push photovoltaic past the cost-breakeven point compared to grid power for rural and even suburban housing loads. And that could lead to enough production to bring in additional economies of scale and drive the price point farther.
This could be big.
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Now I am the Master!(EE)
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I'll default to a "wait & see" perspective, but this has a firm basis in device physics.
One of the major speed limiting factors in microelectronics is capacitive loading. With the tiny scale of contemporary semiconductors "wire capacitance" has become the dominant delay factor. Since the wires are so close together, adjacent wires produce a parasitic capacitance effect(extra load on the circuits) similar to this.
http://en.wikipedia.org/wiki/Parallel_plate_capac
(The article on parasitic cap didn't say much)
As you can see, this capacitance varies directly with the size of the wires, is inversely proportional to the distance between them(shrinking all the time with new process technologies), and directly proportional to the "dielectric constant" of the material between them.
Air has a dielectric constant of ~1.00. Silicon Dioxide, the typical insulator in semiconductors is ~3.9.
http://en.wikipedia.org/wiki/Low-k
Other glass-like materials have been experimented with, but I haven't read about many successes.
So, essentially if you could "leave out" the SiO2 insulating material, you could reduce the parasitic capacitance of the wires by a factor of 3.9. Nothing to scoff at if you can actually pull it off.