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AMD Multi-Core G3MX DRAM Interface Details Emerge
MojoKid writes "New details have emerged regarding AMD's upcoming G3MX technology. The 'future Opteron Platform' AMD mentioned in their press release
seems to be built around a CPU currently codenamed 'Hydra'. Hydra will
still feature an on-die memory controller, but unlike current platforms it will
be geared for DDR3 memory. The processor will interface to one or more
G3MX chips, which
in turn provides the interface to the memory slots. G3MX will act as a memory port extender for the memory controller in the CPU socket and a serial link to the RAM.The electrical signaling between the memory controller and G3MX is based on HyperTransport 3.0."
I didn't even know there was a DDR2. But then again, I'm not a dancing japanophile idiot.
Looks like a mini northbridge - just memory and no PCIe or AGP or anything else.
I wonder what the latency hit is going to be with lots of them on a server and moving data from one branch of a tree to another?
BR> I guess if they don't deviate from HT3 spec too much lots of other applications could emerge for this chip, with the inclusion of partnerships to bring DSP's and other accelerators / CPU alternatives to the server line this is turning more and more into Lego.
Translation: "We've taken some moderately new technology and repackaged it with buzz words to make you think you need it."
When did that start?
It'll be interesting to see if AMD actually get to deliver this technology before they run out of money (http://uk.theinquirer.net/?article=41700)
Despite the propoganda they are not pure angels and Intel is not pure evil either.
Maybe so, but thats not the point. I just dont want to see the mainstream PC processor market to become a one-horse race. If AMD had not been there, Intel would probably still be making P4s clocked at 1ghz today.. Having said that, I dont think AMD can take Intel head on - they are right to (or need to) find other niches..
"A nation that forgets its past is doomed to repeat it." - Churchill
this concept seems quite sensible.
They are using G3MX chips as a sort of multiplexer and connecting it to the CPU though a couple of lanes with high-speed signaling.
Internal logic within HYDRA CPU will have the capability to use either conventional onboard memory controller and drive the DDR-3 RAM directly or when socketed within board with G3MX extenders, use that same lines for communication through the G3MX.
Since the load on the lines will be much smaller and constant and since all lines are unidirectional, each line will be capable of much higher signaling speed, so they will be able to use 4x as much RAM as before per CPU node.
If that is not enough, several Hydra CPUs could be connected through HT links- just like now with existing Opterons.
CPU-G3MX connection is much more direct and probably need not to use extra cycles for node addressing, unlike conventional internode communications through HT links, so time overhead could be considerably smaller...
Also, compared to FB-DIMMs, when accessing to some RAM bank here user only pays some throughput penalty (if any), but doesn't suffer much extra latency- with FB-DIMMs data hos between the modules and each hop costs one clock, so access time for 4-th module is longer than to the first one in a group.
Not to mention that GMX-3 chip could host some L3 cache if needed in some later implementation and that combined speed of all G3MX chips is probably greater than existing solution, so interesting effects could be achieved with meory interlieve.
It could very well be that such combination could have distinct speed advantage even in many workstation applications...
Something bugs me about the chart in TFA.
:-)
It shows 13 lanes outgoing and 20 lanes incoming to each G3MX unit.
And then it references hypertransport. However, hypertransport is a duplex standard. It can transfer data 20GB/sec in each direction per 32bit link.
So how am I to interpret this.
Anyway, supposing that each of those 3GMX units is anything at all similar to an 32-lane HT3.0 protocol, we're talking 80GB/sec of memory bandwidth per processor. That's just nuckin' futz!
C//