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AMD Announces Triple-Core Phenom Processors
MojoKid writes "AMD has officially announced their triple-core Phenom multi-core processor offering, suggesting a triple-threat of processors, from dual-cores to triple-cores and native quad-cores coming to market this year. While the term symmetric multi-processing (or SMP) suggests a balanced approach of multiple cores in an even number of engines working together on a single workload, AMD offers that an odd number of processors can slice at that workload just as efficiently. Time will tell how this architecture will scale amongst various multi-threaded applications and real-world usage models. AMD is definitely moving to make use of these quad-cores that don't quite make the cut by testing them fully as triple-cores and realizing some revenue, rather than throwing them away."
Why Yes. Yes it does. From HERE: Inside, the Xbox 360 uses the triple-core IBM designed Xenon as its CPU. While graphics processing is handled by the ATI Xenos which has 10 MB of embedded eDRAM, its main memory pool is 512 MB in size.
There is no "I disagree" mod for a reason. Flamebait, Troll, and Overrated are not substitutes.
SMP doesn't suggest the number of cores should be a power of two, it doesn't even suggest "even number of cores".
It's about multiple cores processing simultaneously. Check the article I link to, even the damn example diagram has 3 cpu-s.
SMP refers to the fact that all the processors are identical and share the same memory (in contrast to NUMA designs like multi-chip Opteron systems). However, I've seen more and more people refering to cache coherent NUMA designs like multi-core opteron and the upcoming CSI based intel systems as SMP systems which, while a stretch of the definition, is at least reasonable.
Suggesting that SMP has anything to do with having an even number of processors is just DUMB. It may be the case that SMP systems usually have an even number of cores (I don't know) but that's not what the writeup or article seem to be saying.
If you liked this thought maybe you would find my blog nice too:
The picture clearly has a quad-core processor in it. Is this just a binned quad-core processor where one of the cores has a defect (like what Sony did with their Cell chip?)
This is what the article authors suggest, but no, it's a separate architecture. While I suspect it's possible a subset of the 4-core Phenoms to be relabelled as 3-core Phenoms, the bulk of 3-core Phenoms will be built as 3-core parts from the very start.
And, to add insult to injury, this is a quad-core Phenom on the picture, since it's all the authors of the fine article could find. In other words, they are idiots.
I know of at least one 16-core commercial processor. Oh, it runs Linux too.
This post is encrypted twice with ROT-13. Documenting or attempting to crack this encryption is illegal.
The Barcelona/Phenom architecture allows each core (plus the northbridge) to run on its own power plane, and for cores to be turned off completely. Of course, core 0 is the bootstrap processor, so that core has to always be enabled, or they have to have a way to change which one is core 0 before it leaves the factory. Otherwise the BIOS won't be able to bring the other cores online.
The idea of post-factory error detection isn't so far-fetched. If a chip passes QA, the sorts of defects you'll see later in its life are likely to be thermally induced, and the likelihood that the defect will manifest prior to loading of the BIOS is very low. You're not using the MMU or the FPU at all, you're not using much of the cache, you can be running at your minimum power setting, and you're not doing it long enough to heat up much. If a core gets marked bad due to an excess of MCEs, similar to how many systems can mark DIMMs bad on excessive multi-bit ECC errors, the BIOS simply doesn't need to bring it online at boot time. Even if core 0 is the faulty one, you can probably load just enough of the BIOS to bring a good core online and finish booting, since you're not straining it enough to cause thermal problems, and you're only using a tiny fraction of the instruction set and die transistors. This sort of High Availability feature probably won't make it to the desktop right away, but as core counts keep increasing, it's inevitable.
There's no failure quite as dissatisfying as a complete and total solution to the wrong problem.
Firstly, for any general multi-node graph, it's entirely possible for three, four, eight, or any number of nodes to be only one hop away from each other. See fully-connected mesh. For the four-node case, imagine a 2D square, connected on the four sides, plus two links connecting the "diagonals" of the square. In that topology, each of the four nodes are only one hop away from each other. Of course, as the number of nodes increases, the cost of fully connecting them increases, as does the processing cost to multiplex and process transactions into the node from the (n-1) incoming links, but with only four nodes it's entirely possible to create a fully-connected network.
Wiith AMD multi-core processors, all of the cores communicate using a fully-connected crossbar switch in the on-die northbridge - meaning all cores on the die are one "hop" away from each other, including the four-core case. What you're probably thinking of is a multi-socket system that only has two coherent links per socket - that would prevent you from making a fully-connected coherent interconnect for a 4-socket system.
YES!!!!!!
Mod parent up, please, and while you're doing that, read this:
http://www.theonion.com/content/node/33930