AMD Announces Triple-Core Phenom Processors

MojoKid writes "AMD has officially announced their triple-core Phenom multi-core processor offering, suggesting a triple-threat of processors, from dual-cores to triple-cores and native quad-cores coming to market this year. While the term symmetric multi-processing (or SMP) suggests a balanced approach of multiple cores in an even number of engines working together on a single workload, AMD offers that an odd number of processors can slice at that workload just as efficiently. Time will tell how this architecture will scale amongst various multi-threaded applications and real-world usage models. AMD is definitely moving to make use of these quad-cores that don't quite make the cut by testing them fully as triple-cores and realizing some revenue, rather than throwing them away."

Comments

Someone has been brainswashed

[suv4x4]

SMP doesn't suggest the number of cores should be a power of two, it doesn't even suggest "even number of cores".

It's about multiple cores processing simultaneously. Check the article I link to, even the damn example diagram has 3 cpu-s.

Re:Someone has been brainswashed

[suv4x4]

Wait, I missed that, another lie:

However, AMD is definitely moving to make use of these quad-cores that don't quite make the cut, by testing them fully as triple-cores and realizing some revenue, rather than throwing them away.

The triple-core Phenom is an actual Phenom architecture, it's not 4-core rejects. Jesus Christ, NEVER accept submissions from hothardware.com anymore!

That's the worst one in months.

Re:Someone has been brainswashed

[defago]

This is almost that, but still off the mark.

The symmetry in SMP does not refer to the capabilities of the processors. It refers to the relation between the processors and memory.

In symmetric multiprocessors, all processors access the same shared memory uniformly. That is, memory access delays depend neither on what memory zone nor from which processor it is being accessed.

In contrast, in NUMA architectures (non uniform memory access), each processor holds a portion of the shared memory that it can access very quickly. A processor can also access the portions of other processors but this incurs potentially large delays.

At the end of the spectrum, asymmetric multiprocessors combine processors with different capabilities. Here, asymmetric indeed most probably refers to the fact that processors are different. However, while most (all?) actual implementations using a NUMA architecture do use identical processors, they are never said to be symmetric because of the memory access.

SMP Doesn't Suggest Even Numbers Of Processors

[logicnazi]

Here is the definition from wikipedia.

Symmetric multiprocessing, or SMP, is a multiprocessor computer architecture where two or more identical processors are connected to a single shared main memory. Most common multiprocessor systems today use an SMP architecture.

SMP systems allow any processor to work on any task no matter where the data for that task are located in memory; with proper operating system support, SMP systems can easily move tasks between processors to balance the workload efficiently.

SMP refers to the fact that all the processors are identical and share the same memory (in contrast to NUMA designs like multi-chip Opteron systems). However, I've seen more and more people refering to cache coherent NUMA designs like multi-core opteron and the upcoming CSI based intel systems as SMP systems which, while a stretch of the definition, is at least reasonable.

Suggesting that SMP has anything to do with having an even number of processors is just DUMB. It may be the case that SMP systems usually have an even number of cores (I don't know) but that's not what the writeup or article seem to be saying.

Re:A very real reason for using triple-core

[AcidPenguin9873]

In theory with triple core, each processor is only 1 step away from the other processor (consider a triangular setup). With Quad core or greater there's either more bussing or more delays.

Firstly, for any general multi-node graph, it's entirely possible for three, four, eight, or any number of nodes to be only one hop away from each other. See fully-connected mesh. For the four-node case, imagine a 2D square, connected on the four sides, plus two links connecting the "diagonals" of the square. In that topology, each of the four nodes are only one hop away from each other. Of course, as the number of nodes increases, the cost of fully connecting them increases, as does the processing cost to multiplex and process transactions into the node from the (n-1) incoming links, but with only four nodes it's entirely possible to create a fully-connected network.

Wiith AMD multi-core processors, all of the cores communicate using a fully-connected crossbar switch in the on-die northbridge - meaning all cores on the die are one "hop" away from each other, including the four-core case. What you're probably thinking of is a multi-socket system that only has two coherent links per socket - that would prevent you from making a fully-connected coherent interconnect for a 4-socket system.