Intel's 45nm Patch Machinery Exposed
Roboticles writes "Tweakers.net paid a visit to Intel's laboratories in the California town of Folsom, the birthplace of the 45nm CPU. We spoke to lead architect Stephen Fisher about the development of the Penryn chip and the day the first A0 version arrived. We were shown the machinery used to test and patch the 45nm processor, which is currently being manufactured in Arizona for release next month."
I thought the "TickTock" process of developing a technology two different ways was a really neat innovation. Few businesses would dare double their research just to reduce their risks. I wonder if a similar method is used in other industries.
:)
Imagine if Microsoft did it? Maybe we wouldn't end up with things like ME or Vista
I wonder if there's a competitive spirit between the teams.
Yeah, it only conquered the world. :)
"The fight for freedom has only just begun." - Geert Wilders
It's only a win if your execution is bottlenecked by instruction bus bandwidth. That only happens if you're thrashing your L1 instruction cache, and THAT only happens with horribly bloated software and/or horribly small L1 caches.
While it's a good compression of executable code, it's good compression of x86 code. Other ISAs manage to pack way more into their instructions in the first place. Plus, the random alignment of x86 instructions means that the pipeline is elongated by a couple of stages just to find the start of them!
Sorry, but x86 being a nice compression is a half-truth. Other ISAs manage just fine being, for example, fixed 32 bits per instruction and massively benefit from the simpler design. They also tend to be roughly as compact as x86. If you really want to see a properly compressed ISA take a look at Thumb-2.