Sun Niagara 2 CPU Now Open Source

downix writes "Late last night Sun Microsystems announced the immediate availability of the UltraSPARC T2, also known as the Niagara 2 CPU. While we all might not have a silicon fab in the basement, the access to this source code reaffirms Sun's commitment to open source, and in addition gives us FPGA-lovers something new to play with. The source code can be downloaded (with registration) from OpenSPARC.net. Already the previously open sourced T1 has spawned spin-off projects, such as the Simple RISC S1."

Comments

Home fabbing

[QuantumG]

While we all might not have a silicon fab in the basement Does anyone? About how much would such a luxury cost?

Re:Home fabbing

[tlhIngan]

http://en.wikipedia.org/wiki/Fab_(semiconductors) Wiki says over 1 billion, probably close, given the relative rarity of them even amongst commercial companies.

A billion is low-end fabs. High end cutting edge or even near-cutting edge technology costs much more. Maybe a billion for "old-school" tech like 130nm.

No, your best bet is to just pay the few million to have someone fab it for you - there are very few companies that have their own fabs and can do it inhouse (e.g., Intel, IBM, AMD, Freescale (Motorola), Samsung, Toshiba), at least, cutting edge fabs. Low end fabs can be had for cheap (1um and larger), which is great if you don't particularly care about density (e.g., Gemplus - those smartcards have HUGE silicon for 32k memory and not much more).

Most companies are fabless. They contract out the fab work to places like TSMC (amongst others - they're all well known). These include even heavyweight giants like nVidia, Altera, Xilinx and such. The only real downside is that delays can happen if machinery breaks down, or everyone submits a fab order simultaneously that causes backups at the fab and thus delays shipments. The turnaround time (from tapeout to getting chips back) can be 3 months or more. Luckily, most people test their designs out on FPGAs first to work out their bugs before committing them to silicon. Even places like Intel use computer simulation, discrete circuits, FPGAs, and such before they fab it out to their own fabs just because of the turnaround time.

Of course, what I want to know is what's the smallest FPGA one can put this on and still have something workable. (Where things like bus timings and memory clocks still in the realm of "practical" and "in spec").

Re:Home fabbing

[FrankSchwab]

Actually, the cost for one-offs is significantly lower than your estimate.
By using a Shuttle run, where the fab batches together a bunch of designs and runs them through using a single mask set, you can get 20 or so instances of a 130 nm design for roughly $100K. Of course, this assumes that you've already done the layout and verification steps yourself...

I just witnessed a minor miracle, I think

[Anonymous Coward]

Someone corrected the spelling of "Niagra" to "Niagara" - ScuttleMonkey, if it was you, I congratulate you!

Honestly :) Good job!

FPGA Huggers

[Doc Ruby]

in addition gives us FPGA-lovers something new to play with

How big an FPGA would be required to run this? Can you really download the configs and run it on an FPGA at a reasonable speed? Which Xilinx model?

How about running Linux on that simulated Niagara2, like you can uCLinux on a Microblaze? The exciting part would be replacing parts of the OS, like the TCP/IP stack, with "HW" configs for really high performance, customized per app. None of your processes use some dozen instructions? Drop their microcode in favor of a faster multiplier...

Re:FPGA Huggers

[Anonymous Coward]

You can't fit a whole N2 in any FPGA, but one of eight cores will fit and demonstrates the concepts. There is a reason Sun uses a custom LSI fab to build the chip after all.

And no, the FPGA is not terribly fast.

If you just want to run Linux you can do that on a T5120 as is, it works.

Re:FPGA Huggers

[Anonymous Coward]

Forget it. As far as I'm aware, FPGA's are several orders of magnitude slower than dedicated ASIC - which means your Core 2 duo on an FPGA might be the equivalent of running it at about 100 MHz. And that's with FPGA's that are extremely expensive. FPGAs are strictly used to make sure that the CPU works correctly for perhaps the first few hundred million cycles and perhaps some test cases in the middle of normal operation.

Also, your dream of using FPGAs for customized designs are nice, but a pipe dream - first, they're usually too big for a PCI card (at least with decent enough performance). Then it's also hard to correctly design & debug RTL code, which means that it's better to do it in software - by the time you've implemented your super-duper optimized TCP/IP stack, computers have gotten fast enough that the software version is better (and cheaper & easier to maintain).

Also, your basic premise has a much more interesting application; is it possibly to dynamically optimize the hardware via some kind of hardware JIT compiler for the software that's being executed. However, AFAIK, aside from some vapourware announcements, it's still a research topic.

Re:Too bad...

[Anonymous Coward]

Yes, but while the register windows were an interesting research project, my opinion is that they weren't worth the complexity and wasted resources they became. After all, you can only make so many calls before the windows run out and then it's similar to a regular CPU but still paying the complexity of having to dork with the windows. And with so many registers, it probably would have been more interesting to have all of them available to the programmer/compiler than just a small subset (and the compiler could have done windowing on its own if it wanted instead of being forced by hardware) with all the hardware complexity.

SPARCs never were about performance though (although there have been some that had reasonable performance for their time). I also liked the MIPS processors as far as load/store went. Other than that, Alpha was OK. I cut my teeth on the M68K family so I guess I'll always like them :)

I worked with Suns from the 3/50 days, 4, and then SPARCs up until the UltraIIIs (desktops and servers). I always liked the machines (they were usually very stable, there were notable exceptions but most of the time they were solid machines). Good workhorses but not necessarily racehorses.

I actually have the spindle/platters from an old IPI drive (500M or so, IIRC) sitting in my living room, pulled out of drive when we were decomissioning all of our IPI drives.

Re:Is the hardware any good though?

[jd]

Then I guess one area that open source hardware nerds can work on is to rework the FPU to be faster. If people can load the files into an FPGA and get comparable results on maths-heavy software to a full hardware implementation of the T2 as it stands, I would imagine the scientific computing folk would go for the FPGA solution as it would be cheaper so they could build more nodes for the same amount of money.

Sun is a lot of things, some unprintable, but stupid isn't one of them. If it can be shown that a T2 with stronger maths will sell better than the T2 as-is, then you will see a T2 with stronger maths in very short order.

There are other things Sun could include in the processor. I am, to this day, a devoted fan of direct CPU-to-CPU channels for multi-processor systems. Inmos' Transputer let you build hypercubes of processors as large as you liked without scaling issues. Xyron's ZOTS also seems an interesting technology, even if nobody uses it at this time. The potential wishlist of things that could be added without wrecking the design is large. Given that the core is GPLed, it would seem to make sense to experiment with some of those ideas. See what would actually work in practice, with the possibility that some vendor (not necessarily Sun) will chase the idea and turn it into a reality.

Re:Too bad...

[downix]

Well, that "too complex" windowing capability is one of the reasons why the Niagra core can run 4 threads simultaneously. It has 4 windows, and swaps them automatically, enabling a deeper pipeline without breaking the ISA. So, the compiler sees ALU's rather than 1.

In addition, I rolled my own 32-bit SPARC once with only 2 register windows, with the compiler did not control. What you had was a "program" window and an "interrupt" window. So when interrupts happened, rather than having to save the register state before dealing with it, you immediately switched windows and bam, have a completely clean slate of registers to work with.

Re:21st century business plan

[jcnnghm]

Hardware. I transitioned all of my company's servers to Sun (when they started selling x86 servers) over the last few years, and I couldn't be happier. The equipment is more expensive, but it is also of a superior quality and features real enterprise management features. Opening up Solaris had a lot to do with my initial decision, and I wouldn't be surprised if we don't transition to the T2 in the future. Since all of our servers are virtualized anyway, it isn't really a bad idea to move lots of small servers to a few big servers, and this open architecture will undoubtedly give some experts the opportunity to publish very in depth analysis of the chips.

Re:Is the hardware any good though?

[dr2chase]

(disclaimer, I work for Sun, but I manage to be completely clueless about many things, including the official names of Sun's products)

Niagara 1, had one FPU per chip. Niagara 2, has more than one.

The way you pose it -- doesn't perform unless you can find the parallelism -- is not the right way. Some clever person found a market where there was parallelism, and that turns the problem around. "Given that I have all this work to do, what's the throughput per watt?" Niagara wins there. And it happened that those people, or a lot of them, didn't have a burning need for floating point.

Or to use a lame car analogy, a schoolbus is no good unless you can find 32 kids to haul, whereas a minicooper is cool and zippy with only two. But if you regularly have 32 kids to haul, and some people do, you want a schoolbus, and a minicooper is not very efficient.

Re:FPGA lovers

[nahpets77]

You may not be able to use them at home, but most university labs have expensive FPGAs lying around collecting dust. This is good news for people doing research at universities, where they often like to tinker with the hardware to try out new ideas.

Sun is the new Bell Labs

[teknopurge]

I've had this position for about 2 years now.

IMO, Sun is one of the only companies left innovating.

-Google is just rehashing old ideas.(Gmail? come on....I had webmail 10 years ago.)
-Oracle(eh... RDBMS v45.2 anyone?)
-IBM(If I see one more pointless black-and-white commercial about "ideas" I'm going to scream. IBM should listen to their marketing department and instead of telling us to "Stop thinking, start doing" they should create something that isn't AIX)

And, I will be the lone voice and dare to say that Microsoft, yes them, has a few teams that are starting to 'get it'. Apple is doing a great job with human-computer interaction.

Show me new, for I am tired of your old.