IBM Leaks Details on New Mainframe

Mark writes "Big Blue inadvertently revealed details about its new z10 Enterprise Class mainframe set to launch on Feb. 26, as well as details on z/OS v1.10, a new version of the mainframe OS due out in September. 'According to an internal IBM document obtained by SearchDataCenter.com, the z10 Enterprise Class will come in five different models and feature 64-way chips, compared with the 54-way z9 mainframes and earlier 32-way models. In a conference call last month, IBM CFO Mark Loughridge told investors that the z10 would have 50% more capacity, which indicates that it will probably tap out at around 27,000 million instructions per second (MIPS) at the top end, compared with about 18,000 MIPS on the previous z9 Enterprise Class.'"

Comments

Re:This might be a dumb question...

[avalys]

MIPS stands for millions of instructions per second, not mega-instructions per second. We'd have to talk about billions of instructions per second, or BIPS, and that sounds lame.

Re:Kinda slow, eh?

[dedazo]

The day you can use commodity hardware to build a failover-capable sysplex running multiple instances of an OS that can run 30-year old COBOL applications that do millions of financial transactions per minute with absolute 24/7/365 uptime, you'll be a very rich man indeed.

In the mean time, IBM, Hitachi and a few others will be raking it in for you.

Re:Except the processor...

[TheRaven64]

I've seen that before, but the POWER6 is not the convergence chip. They share a lot, but it's stuff that matters from IBM's perspective (lowers development costs), not from their customers' perspectives (allows them to run the same software). That said, the biggest difference between the POWER6 and the z6 is the instruction decoder (addressing modes are easy to switch - look how many the Core 2 supports). Instruction decoders tend to take a roughly constant number of transistors. One of the big wins for RISC chips was that they could have simpler decoders and dedicate a lot more transistors to execution units. Now, the decoder has gone from being 50%+ of a CISC chip to under 10%.

It wouldn't surprise me if the POWER7 either implements a superset of the POWER and System Z architectures, or has switchable decoders. Considering the fact that it's already possible to hot-plug CPUs on systems at this level, I can imagine a future IBM line where the hypervisor allows you to not only partition the system, but also decide which chips run in POWER and which in System Z mode dynamically, migrating virtual machines and restarting CPUs as required. That could be very attractive for customers wanting to consolidate mainframe, AIX, and Linux systems.

One of the design goals of the PowerPC instruction set (a superset of which is implemented by the POWER6) was to easily emulate x86. It would be really interesting if IBM would enhance this emulation support into the hypervisor, allowing customers to run legacy x86 Linux, Solaris or Windows Terminal Server virtual machines on their mainframes.

By the way, this mainframe is one of the big reasons why IBM are so keen on open source. If you run Linux and (portable) open source software then IBM can sell you a mainframe running Linux VMs when you start to outgrow your current infrastructure. The reason IBM owns so much of the (small, but incredibly lucrative) mainframe market was that in the '60s they pushed the predecessors to this system - System/360. They sold cheap minicomputers and high-end mainframes that ran exactly the same applications (and, with System/370, the mainframe could even run virtual minicomputers). They got people using the cheap minis and then presented them with a clear upgrade path. With open source, they can give people a really long upgrade path starting at commodity hardware and going as far up as they want.