Researchers Design Microchip Ten Times More Efficient

WirePosted writes to mention that a new highly efficient microchip has been announced by researchers from MIT and Texas Instruments. The new chip touts up to 10 times more energy efficiency than current generation chips. "One key to the new chip design, Chandrakasan says, was to build a high-efficiency DC-to-DC converter--which reduces the voltage to the lower level--right on the same chip, reducing the number of separate components. The redesigned memory and logic, along with the DC-to-DC converter, are all integrated to realize a complete system-on-a-chip solution."

Comments

Any chance of commercial success?

[damn_registrars]

The first thing that came to mind when I saw this article was the Transmeta Crusoe processor. Which unfortunately never achieved much of any significant market penetration. Indeed, it seems that you really have to have something more than just an incredibly efficient chip in order to compete against the Intel - AMD behemoth.

Personally, I would love to see a chip that requires very low power make it into the mainstream market. I think it would great to have something like that for the miniITX form factor or something of that nature that hobbyists could tinker with and find fun applications for. The Transmeta, unfortunately, never realized that as far as I ever saw.

Re:Any chance of commercial success?

[ejtttje]

I don't think they're demonstrating a particular CPU, but a technology or design strategy that can be built into *any* chip. So Intel or AMD could pick up this research with their own chips. (subject to patents and licensing of course)

Also, from the article: "So far the new chip is at the proof of concept stage. Commercial applications could become available "in five years, maybe even sooner, in a number of exciting areas," Chandrakasan says

Interesting but what about variability?

[quo_vadis]

Their work is definitely interesting, but I think some important questions remain unanswered, the main among them is the tradeoff between correctness of operation vs. performance because of variability. There is a paper in ISLPD 2006 which shows that for a 65nm circuit to operate at 0.3 V, the clock period must be scaled up by a factor of at least 230% to compensate for variability related issues. Additionally, there is a huge problem as far as tool support goes. This is not just mix-and-match style design. In order for this to have widespread use, it needs to work well in the EDA tool workflow. This means that libraries (and to some extent transistors) need to be characterized well at the subthreshold operating voltages. This causes a catch-22 situation. In order to design something using this subthreshold voltage technology, you need good transistor models, but the fabs have no interest in providing these models unless there is large customer demand. It is pretty expensive to get good models. The way this works is most fabs actually create transistors/gates at the given feature size, characterize them, including parameters for variation/process variability and give these to their customers, who design their chips based on these simulations. The reason these are so important is that for synchronous circuits, you have to base the design of the clock scheme on the worst/average case delay, and this you can get only by doing complete (usually Monte Carlo based) simulation of the chip using the transistor models that fab gives you. If you base the parameters solely on simulation based tools, you ignore all sorts of effects in the real world, causing a massive drop in yield(i.e. working chips made by fab).

Re:Will we get these soon?

[crgrace]

Putting a power amplifier on the same chip as a radio transmitter has not been successful. A lot of money has been wasted going down that road so far...

I could use those converters.

[jcr]

If they have a substantially better DC-DC conversion technology, that's worth a lot of money to a lot of people already.

-jcr