Tilera Releases 64-Way Chip Dev Tools

eldavojohn writes to tell us that Tilera has released a Linux-based development kit for their 64-core system on a chip. "The Tile64 is based on a proprietary VLIW (very long instruction word) architecture, on which a MIPS-like RISC architecture is implemented in microcode. A hypervisor enables each core to run its own instance of Linux, or alternatively the whole chip can run Tilera's 64-way SMP (symmetrical multiprocessing) Linux implementation. An 'iMesh' switching interconnect, developed by Tilera's founder, MIT professor and serial entrepreneur Dr. Anant Agarwal, is said to eliminate the centralized bus intersection that limited scalability in previous multicore designs."

Comments

Re:Licensing containment barrier??

[quarrel]

> It definitely sounds like a performance hit if it's turned on.

No, if anything they pitch it as a performance gain.

The idea is to run Linux (or OS of your choice), with various control plane functions (it can have an IP address, you can do config, stats collection etc etc), on say (making up these numbers!) 4 of the cores, while the other 60 cores are running without an OS (they offer a BIOS like environment with basic functions to get access to the backplane and subsequently the packets) doing data-plane functions, perhaps doing deep-packet inspection for QoS delivery, security functions (IPS?) etc.

The Linux side, particularly the kernel isn't going to contain your real IP, while the data-plane side is all your secret-sauce. It involves embedded style programming without lots of OS support, but you get speed and the networking vendors are used to this sort of model - it sure beats the hell outa doing it in an ASIC on the dataplane side which is what they're used to.

This isn't an attack on open source - it's using it in a sensible fashion IMO. However, for the paranoid types who've seen the fud, they probably pitch this split of operations as a "licensing containment barrier" cause a marketing person thought it might help somewhere.

--Q

Simple version.

[jd]

They have set up an 8x8 grid of processors, not unlike a chessboard. Each square on this grid can talk only to adjacent squares (up, down, left, right), with the edge squares connecting to I/O devices. They refer to their network as a mesh, but the correct term for this design is a Manhattan Network. This is not significantly different from a processor I dearly loved in the late 80s, the Transputer. That, too, had 4 connections from each processor, but you were not restricted in how you connected the Transputers together. A grid, it transpired, was not efficient, you needed to arrange the connections to form a hypercube. (Yes, it's 2D, so it's actually a 2D representation of a hypercube. Now stop fussing or I won't get you that Beowulf cluster for Christmas.)

I like the idea, I like the idea a lot, but the fact that they opted for a simple but slow topology doesn't fill me with hope. Especially as they suggest running SMP over it. Processors close to the centre of the "mesh" will be resource-starved. There needs to be strong affinity of a given thread to a given core, where the weighting is by the operations expected and where that weighting can (and will) shift as code blocks change or new threads start. In other words, you want something that is semi-static, semi-dynamic according to need. Only the OS is capable of obtaining that kind of information, so it is the OS that needs to do the dividing, NOT the architecture underneath OR a system administrator.