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Scientists Pave Way For 25nm CPUs
arcticstoat writes in with word that scientists at the Space Nanotechnology Laboratory at MIT have found a new way of extending Moore's law into the future — they have succeeded in etching a grid of 25nm lines into a silicon wafer. The article notes that this technique could be used for writing the grid on which chips are laid down, but that the electronic elements would have to be written using more complex techniques. "[Researchers] created an interference pattern using light from a laser with a wavelength of 351 nm. The pattern consists of alternating light and dark zones repeating every 200 nm. This allowed them to etch 25-nm lines into a silicon wafer, each 175 nm apart. They then repeated the process three times, each time shifting the interference pattern by 50 nm and etching another 25-nm groove. The resulting grid has alternating 25-nm stripes and grooves..."
Altera (www.altera.com) are one of the many silicon companies announcing 42nm devices shipping in the next year or so. Xilinx fanboys - I'm sure they promise the same (picture an AMD/Intel bunfight if you will) - though I must confess I am friendly towards them as an ex employee of sorts, I am certain they are not the only ones proposing to produce devices at this process node in the near future. Intel and IBM being very much at the front of the curve, so to speak. The gap between theoretical limits being announced and actual manufacturing at the announced node seems to be getting a lot shorter. Is quantum really next, or is optical? As we get down to 32nm and beyond the so called 'moores law' (which seems only to really serve journalism as such ;) ) seems to really, genuinely be nearing the limits. What IS next after silicon transistors on a die? Gallium is supposedly running out (due to flat panels) and that's only a doping chemical for speed, still in the silicon domain, not a real sea change of technology. Whats going to happen to the size/power curve? Even multicore processors will suffer as long as they are still roadmapped out on the same substrate. Are we really running out of time now? I don't really hear of the 'next big thing' in any form other than conjecture at the moment..?
I've laid floating lines 1 nm apart with my boat in the past. 25 nm could be done if you wanted but that's getting pretty far apart. Who wants this grid, and why the heck would you use a laser to create light and dark zones every 200 nautical miles?
First, IAALE (I am a lithography engineer) working on Intel's 22nm process technology. Let's clear up a few misconceptions:
1) The name of a logic node is directly related to the size of the features being made. Those names (e.g. 65nm, 45m, 32nm, etc.) used to relate to the "half-pitch" of the minimum pitch that was printed. But that is not true today. 65nm used a minimum pitch of ~200nm, 45nm used ~140nm and 32nm is using ~100nm. The next node, 22nm is slated to use minimum a pitch of 72nm. The features discussed in this article have a pitch of 50nm, which would be equivalent to the node after 22nm, i.e. 16nm.
2) It's not hard to print features smaller than the wavelength of light. For the lens based systems we used, the Rayleigh criterion gives the minimum pitch possible: 0.25*lambda/NA, where lambda=wavelength (193nm) and NA=numerical aperature (1.35 for the best lenses). So 72nm is the minimum pitch, already much smaller than the wavelength
3) I hate to break it to these researchers, but interferometry has been used for a looong time to make gratings. Search for "interferomety lithography" on Google Scholar. The fourth link is called "Nanolithography using extreme ultraviolet lithography interferometry: 19 nm lines and spaces". That paper is from 1999. And they did that one exposure, not three (using a smaller wavelength).
You would actually need at least one more exposure to divide the grating into something that resembled a logic circuit. The technique in this artcle is not practcal for a number of reasons, but we can do better than them using pitch-doubling techniques and only two exposures.