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SATA 3.0 Release Paves the Way To 6Gb/sec Devices
An anonymous reader writes "The Serial ATA International Organization (SATA-IO) has just released the new Serial ATA Revision 3.0 specification. With the new 3.0 specification, the path has been paved to enable future devices to transfer up to 6Gb/sec as well as provide enhancements to support multimedia applications. Like other SATA specifications, the 3.0 specification is backward compatible with earlier SATA products and devices. This makes it easy for motherboard manufactures to go ahead and upgrade to the new specification without having to worry about its customers' legacy SATA devices. This should make adoption of the new specification fast, like previous adoptions of SATA 2.0 (or 3Gb/sec) technology."
Why? Do you have a hard drive that can even saturate a SATA I bus?
Not a typewriter
where there are multiple INDEPENDANT heads reading/writing on multiple platters all at the same time
The entire idea of 'heads' should be forgotten. Mechanical drives should be sent to oblivion and we should welcome your idea of parallelism on solid state solutions.
Fact: Everything I say is fiction.
And what you clearly missed from the post you're responding to is that the clock rates that you can get from serial are so much higher than what you can do with parallel that it more than offsets the disadvantage of serialization.
There are two things that limit the speed of parallel interfaces. As the GP mentioned, one is signal skew. The clock rate has to be slow enough so that the receiver can sample all data lines at the same time and get them all within the data eye. The second is that the data lines are single-ended, meaning that there's only one wire per signal. The clock rate has to be slowed down to ensure that the signals have reached full on or full off at the other end and that they're noise free.
High-speed serial interfaces use DIFFERENTIAL SIGNALLING. The signal is transmitted over two wires that switch in antiphase. You decode them by comparing them. This has several beneficial effects. One is that noise affects them the same, so even if they're both offset by noise, they compare the same. The other is that now you don't have to wait as much on the effects of resistance, capacitance, and inductance. You can reliably decode the signal before the transitions are complete. (Look up "slew rate".)
So, using the same basic silicon technology, you can get a single differential pair to transmit data MUCH faster (in bytes/sec) than you can with parallel. It's interesting to see how technology transitioned from serial to parallel (wider means more bits per second), back to serial. The reason they didn't just stick with serial was that they just didn't have the technology to make the I/O drivers go that fast until recently.
IIRC, A 1x PCI Express channel is a single differential pair for data. (I think there's a side band channel and some other stuff.) This is just like DVI and SATA. 16x PCI Express is sixteen 1x channels. The trick here is that although data is interleaved across all 16 channels, those channels are not syncronized with each other. They are out of phase, and the the data is just put back into phase at the receiver.
Well, this may not be exactly what you were getting at, but I'd like to split hairs here anyway, and divide this into two separate issues that SATA/SAS resolved.
For best results it's important to model the cable as an RF transmission line, with a specific impedence. An ideal transmission line has the important qualities that all the energy you send from one end will arrive at the other, and none will be reflected back to you. To get reasonably close to this ideal, we space the wires we use a fixed distance apart (in relation to the wire's diameter), choose our dielectric (insulating material) carefully, use terminating resistors at both ends, and keep the line a simple line (no tees, etc.)
For those of you who cut your teeth on parallel SCSI, 10base2/10base5 Ethernet, or Apple LocalTalk, you'll wax nostalgically at just how much of a pain in the ass this was.
For those of you who have only messed with parallel IDE, you'll wonder why you never had to deal with this. The reason is that IDE cheated a little bit - they only terminated the controller (motherboard) side of the bus, and let the signals reflect off the other end. This left only a master/slave/cable-select jumper to infuriate you - but it also limited how long an IDE cable could be and prevented them from jacking up the clock rates on it.
SATA/SAS fixes this for good by limiting you to one device per cable ("port", not "bus"). Both ends are hard-wired to always terminate and any cable problems are limited to a single drive.
The other issue you may have been referring to is balanced (differential) vs. unbalanced signalling (where one wire is held to ground and the voltage read off the other wire). Electrical engineers do commonly call unbalanced signalling one wire because ground is so boring that they never bother to connect it on their schematics, but it does have to be connected in real life and coax Ethernet/most old SCSI/Parallel IDE/RS-232/VGA still used two wires per signal. Balanced/differential signalling (LVD/HVD SCSI, SAS, SATA, 10/100/1000baseT, USB, telephone lines, T1 lines, LocalTalk, etc.) allows for the can't-imagine-life-without-it common-mode noise rejection technique you describe.