Slashdot Mirror
VHDL or Verilog For Learning FPGAs?
FlyByPC writes "We're in the first stages of designing a course in programmable devices at the university where I work. The course will most likely be centered around various small projects implemented on an FPGA dev board, using a Xilinx Spartan3-series FPGA. I have a bit of experience working with technologies from 7400-series chips (designing using schematics) to 8-bit microcontrollers to C/C++. FPGAs, though, are new to me (although they look very interesting.) If you were an undergraduate student studying programmable devices (specifically, FPGAs), would you prefer the course be centered on VHDL, Verilog, a little of both, or something else entirely? (...Or is this an eternal, undecidable holy-war question along the lines of ATI/nVidia, AMD/Intel, Coke/Pepsi, etc...?) At this point, I've only seen a little of both languages, so I have no real preference. Any input, especially if you're using one or both in the field, would be very helpful. Thanks, and may all of your K-maps be glitch-free."
I work at a chip company doing ASIC and custom SOC microprocessor stuff. We mostly use verilog here for our stuff. Most of the VHDL I see comes from customers, which often gets blended into our verilog platforms. All our RTL IP cores are verilog that I know of, at least that I've used/seen, and our integration work to make platforms out of all the IP pieces is verilog. What we synthesize to gates is also a verilog gates netlist result that goes to place/route into silicon.
In college the class I took that involved this sort of thing was in VHDL, and I hated that. had me really nto wanting to do this kind of work, I was really happy when I was exposed to verilog and I didn't hate it, and I've been a chip guy for over 10 years now.
But as I understand, VHDL is far more popular in some locations, and verilog in others, so jobs in other locales may be completely opposite to my work environment. It would probably be nice to show some of each to be a little familiar with both such as comparing/contrasting = to = and == to ===, but focus on one or the other for people to really get experience fitting pieces together and learning the general stuff about RTL design, etc. that are not as dependent on what language you use.
I've worked at several top chip companies in Silicon Valley, in graphics and telecom industries, and they're 100% Verilog. I also suggest learning System Verilog as well, especially for testbench development.
My university has been very successful using VHDL in our intro embedded programs. Check out this book on VHDL programming: http://www.amazon.com/VHDL-Digital-Design-Frank-Vahid/dp/0470052635
In many ways schematic capture is an easier first step. You can hold off on Verilog or VHDL until you have made every flavor of flip-flop yourself. If you can get logic that has a few to several dozen gates to work first, then you can consider an HDL. And it doesn't really matter too much. There are pros and cons to each, and different industries prefer different languages. Actually different regions of the world prefer different languages too. Verilog is extremely popular in Silicon Valley, but on the East Coast you will find a lot more people using VHDL.
Many who prefer one over another do so because of features for doing verification. Until you know what verification is all about you probably won't be able to make an informed decision.
This fact makes it easy for most people: Icarus Verilog is open source, free and multi-platform. And useful for doing verification work, and also is capable of generating netlists to use with your favorite Xilinx or Altera parts. I'm not saying it's amazing or anything, but it does have some advantages for a hobbyist doing small projects.
“Common sense is not so common.” — Voltaire
There were very good reasons why people used VHDL in the past. Because VHDL was an open language before Verilog, the cost of VHDL tools was historically lower than Verilog tools. Since this cost was much more important to FPGA designers, VHDL tended to dominate the FPGA market.
On ASIC side, the first mainstream commercial synthesis tool was Synopsys and Synopsys chose to support Verilog before supporting VHDL. Amongst all the other NRE costs in designing an ASIC, the added cost of using Verilog tools (instead of VHDL) was not really significant. Also, tools to support large designs advanced initially as Verilog tools.
Fast forward few years and Verilog is now open, the cost differential has now disappeared. However, VHDL had a lot of features related to design validation that were not in Verilog. In VHDL you can read and write files. Such things as configurations are supported, etc.. This type of capability makes it easier to write a testbench in VHDL, while on the Verilog side, additional tools and languages are commonly used.
Fast forwards a few more years to today and now we have System Verilog. This gives Verilog the capabilities that it lacked in comparison to VHDL and probably more. The price of VHDL tools is the same as Verilog tools.
Summary: it's clear that the future does not belong to VHDL. It looks like System Verilog is the future, although there are other contenders. So, if the choice is between VHDL and Verilog -- pick Verilog.
The real "Libtards" are the Libertarians!
We were introduced to VHDL in our University's Digital Circuits course.
Most of the above commenter's have mentioned that Verilog is C like, I personally have never used or programmed in Verilog so I can't comment on that.
I did however like VHDL very much, particularly because it was *different* from C, I'm kinda growing tired of C like languages and VHDL was a breath of fresh air. It made FPGA's and the entire course in general a whole lot of fun.
It's strong typed nature was a bit cumbersome at first especially with converting std_logic to std_logic vectors and such because we weren't really shown how to do this or given a syntax/library reference like MSDN or Java's Documentation site.
So I'd say make a good introduction to Entities, Ports and Architectures, explain Process, Signal and Constant statements very well, also particularly highlight the strong typed nature of VHDL.
I think most of your students (such as myself) will not have done any programming in a true strongly typed language before, so this will be bit of a shock, and getting those conversions will be frustrating. (I have been there, Googling really does not help all that much)
I hope your students get as much fun out of that course as I did.
Cheers,
filereaper.
VHDL and Verilog each have their strengths, which is why neither has been able to supplant the other. Perhaps in the long run System Verilog will change this (bringing much of the power of VHDL to the Verilog world), but that day hasn't arrived yet.
Verilog code tends to be very concise, with the language making some implicit conversions and assumptions that turn out to be correct most of the time.
VHDL is bigger, bulkier and more rigid. The rigidity can be annoying, but it also is good at catching errors. The language has features that allow for very elaborate testbench construction, and some powerful means for abstraction (the generate statement, multiple architectures for an entity, etc). But this power comes at a cost. The spec for the language is several times larger than for VHDL. At one point I had a Verilog quick reference that fit nicely on a single page. My equivalent quick reference for VHDL covered four pages.
I've gone through the "choose an HDL" process twice, and both times selected VHDL. But that was within the context of at least half the team already being fluent in VHDL, and working on a large enough (and long lived enough) codebase that we could take advantage of some of VHDL's power. I wish VHDL wasn't so cumbersome and verbose, but it was still a win overall.
You are in a very different situation. I'm assuming you have minimal experience with either language, and it will be new to your students as well. You're going to have plenty of other things to be worrying about (digital design, synthesis, debugging, etc). I think Verilog is a better choice for your situation. It's going to do everything you need, and not really get in your way.
Also, don't worry about which tool is more popular in industry. Tools change many times over a career. University classes should be about providing good theory and foundation, so pick whatever tool enables you teach those concepts most effectively.
I've not programmed in HDLs but I've read some of their programming. All the companies I've been at has used VHDL, though very often the main developers will gripe that they'd rather be using Verilog...
I'd agree with the assessment that if this is for students, then always teach the more rigorous language first. This goes for programming languages too. If you teach what is popular today, you end up with graduates who have difficulty adapting in the future. VHDL is the more rigorous and formal language, which is precisely what it needed with hardware design.
1) The syntax is incredibly similar to C. Which is why it is always described as "C like" to people who have very little experience in HDL.
The operators are the same as C operators, the comment style is the same and there are semicolons. That is the full extent of the similarity with C. The are no braces (well, there are, but they don't mean what they do in C), macros are different, constants are different, assignment can be different, functions aren't functions, switch statements are case statements, etc, etc... saying that Verilog is "C like" is only going to confuse people who know C. Verilog has more in common with VHDL that with C really (begin and end statements, two difference types of variables, two different ways of doing assignment, both languages have constructs with no C equivalent) and yet people only say Verilog is "C like".
VHDL is better if you absolutely must have full control of the resulting performance on the FPGA.
Ok, I'll bite - what does VHDL give you control over that Verilog doesn't?
It's not exactly rocket surgery.
Now having said all that... System Verilog has a LOT going for it, and when the tools catch up to the Language Reference Manual, then it could be an extremely powerful design language. This presentation from DATE 2004 shows why. http://www.systemverilog.org/techpapers/date04_systemverilog.pdf
"VHDL was created by hardware engineers who know nothing about programming languages. Verilog was created by computer scientists who know nothing about hardware."
Ummm, no.
Oops, I got the quote backwards (duh), you're right (obviously).
Disclaimer: I've been using VHDL design & verification for ~10 years (but also Verilog, and Specman E, PSL, etc.) & I'm a bit of language geek
VHDL is more verbose, but more capable than Verilog. There are several points that in my opinion make VHDL a better language for teaching (and for design and simulation):
1. It's *MUCH* harder to shoot yourself in the foot than with Verilog. VHDL is strongly typed (which is partly why it's more verbose) and generally when you write code you're not going to run into weird problems. Verilog is a minefield by comparison. Even very simple code can have race conditions & may synthesize differently from how it simulates. When I took a Verilog course many years ago, the first thing they handed us was fridge magnet with 7 rules (do/do not). If you don't follow those you risk shooting yourself in the foot. Nothing like that is required of VHDL.
2. VHDL is a lot better for simulation than Verilog. Partly because of Verilog's problems, once you step away from the RTL design subset you run the risk of spending hours debugging stupid things that a VHDL compiler would've caught, or that wouldn't happen in VHDL. With VHDL you can write very sophisticated testbenches(1). As an example I've written some constrained random + coverage testbenches in the style of Specman (or SystemVerilog). Try doing that with plain Verilog.
3. Verilog is a very simple language. It's harder to write reusable code. It's much easier to create parameterized, scalable, reusable blocks in VHDL through the use of generics and generate statements, multi-dimensional arrays, etc.. In fact this is my default style in VHDL. If it can be parameterized it should be. This applies especially to FPGA designs where the design requirements are typically more fluid than in ASIC designs. Also making designs parametric forces you to think more deeply about what you're implementing and to get to the core of an idea which in my opinion leads to cleaner, more maintainable code (again IMO a big deal for FPGA designs)
Having said all that:
1) VHDL seems to be on the wane a bit and the bastard child of Verilog, a.k.a System Verilog seems to be everyone's favorite language. There are definitely benefits to System Verilog. It's a much better language than Verilog. The problem is that it is based _on_ Verilog and shares many of the problems.
2) As has been mentioned above a good designer should be able to pick up a new language quickly, especially the design subset and a seasoned designer should at least be able to read both languages. You _will_ run into both of them in your work even if your shop primarily uses one.
3) It's true that ASIC designers tend to use Verilog, while FPGA designers seem to favor VHDL
(1) BTW the reality is that if you're doing your job as a designer right, you spend *way* more time writing testbenches than writing synthesizable RTL
It's been about ten years since my TAs and I taught the lab section of the advanced digital logic design at my university. I agree that, generally speaking, VHDL is a better teaching language than Verilog. Part of the reason is that Verilog, being much like C, is inherently procedural. You don't want to think procedurally with digital logic except for the specific case of state machine design, and even then you have to take into account concurrency. It is this fundamental aspect of concurrency in HDLs that is key to being able to design effectively. I can define twenty clocks going into counters, just like I can wear twenty watches on my arm and have them all tell time independently and/or at different speeds. You can't really do that with procedural languages unless you're talking about thread scheduling, and then this becomes a thread scheduling exercise when you have multiple threads. Even then, you will never be able to get the speed of digital logic because you have instruction fetch, instruction decode, etc. that introduce latency that cannot be reduced even in a multi-core CPU. Not thinking procedurally will help, and the strong typing of VHDL over Verilog will help greatly in my opinion. Those Karnaugh maps you talk about are fine to learn, but HDLs use case statements in VHDL that make state machine design trivial especially when you have >8 states.
Beyond HDLs, however, are FPGAs and ASICs (and I've designed using both). Putting the differences between FPGA and ASIC aside, FPGA has some very specific ties to the vendor because of the way the FPGA is architected. Assignment of I/O, synthesis, and most of all timing constraints for guiding the "map place and route" tools for FPGAs are something you won't learn from VHDL alone (e.g. clock domain frequencies, max/min delays, input/output delays, false/multicycle paths, setup and hold times or worst-case timing paths in the design). These are essential to digital design, but not part of the HDL at all (see Synopsys SDC format for more info). In fact, shell scripts, sed/awk, Perl, TCL, Scheme and Python are also essential to know because they glue the various different tools together through scripting, processing of text files, tailing log files, and batching can be critical to being efficient. So is being thorough in understanding log file warnings and errors, timing reports. Electronic Design Automation or EDA tools also have their own idiosyncrasies, and you'll need to develop a stable "reference front-end and back-end design flow" if you haven't already. Do you use an Altera or Xilinx reference board, or an add-on PCI-based FPGA card? And how do you analyze what's coming and going at the interface? All of these questions need to be answered before you really get going on FPGAs. ASICs have an order of magnitude more complications for reasons I won't even discuss, but it just gets harder. So those state machines that you created without K maps will have synthesis pragmas that direct the compiler to create the appropriate state machine (e.g. One-hot for performance, Gray code for lower power, etc.).
Finally, there's the work world. As other posters have mentioned, North America is primarily focused on Verilog while the rest of the world is VHDL. Most synthesizable IP cores for various functions come as Verilog. So, the truth is, you should know both major HDLs, but you would be better off being proficient in Verilog in the real world for the simple reason that it is the present and future (or at least its successors, such as System Verilog, are the future) are for many reasons. Also, in the work world, it's critical to know the major EDA vendor software and to put it on your resume (i.e. Mentor Graphics, Synplicity (for FPGA), Synopsys, in roughly that order, and Cadence and Magma for ASIC) as well as all those scripting and other languages like Perl and TCL that I mentioned. Don't completely ignore VHDL, however.
As an ironic point, there are SystemC compilers for hardware that are becoming more and m
Nonsense. Teaching the tool is the job of a vocational program. The theory of HDL will long out-last any particular errors or syntax that come about.
Except in this case the tool is intricately related to the "theory of HDL". This isn't some "sorry, you used \r\n instead of \n" issue. VHDL compile errors are real design issues. Basic issues that every designer needs to understand.
Example:
integer count;
bit [8:0] bus;
always @(posedge clk, negedge reset) begin
if(reset == 0) begin
count = 0;
end else begin
count = count + 1;
end
end
assign bus = count;
This is all legal in Verilog. Its equivalent VHDL would throw a huge fit. Does the student who uses Verilog for this understand how it will be translated? Design Compiler will do the following things "behind the student's back" with a list of warnings inside the log that most undergrads won't bother looking at:
1. It will assign "bus" to the first 8 bits of count. This may or may not be the desired behavior.
2. It will treat count as a signed integer, it's probable that it is meant to be an unsigned counter.
3. It will optimize by encoding the counter in something other than BCD. The ambiguities of how the bits of "count" are assigned to "bus" with the encoding scheme of choice are non-obvious.
VHDL makes you explicitly describe all of these things. It may seem a "pain in the ass" but these concepts are ones that any designer should understand *before* they commit something to silicon (or SRAM in the case of Xilinx).
After you understand all of this, moving to Verilog will save you time (as long as you're careful) by letting the compiler do more of the manual translations for you.