VHDL or Verilog For Learning FPGAs?

FlyByPC writes "We're in the first stages of designing a course in programmable devices at the university where I work. The course will most likely be centered around various small projects implemented on an FPGA dev board, using a Xilinx Spartan3-series FPGA. I have a bit of experience working with technologies from 7400-series chips (designing using schematics) to 8-bit microcontrollers to C/C++. FPGAs, though, are new to me (although they look very interesting.) If you were an undergraduate student studying programmable devices (specifically, FPGAs), would you prefer the course be centered on VHDL, Verilog, a little of both, or something else entirely? (...Or is this an eternal, undecidable holy-war question along the lines of ATI/nVidia, AMD/Intel, Coke/Pepsi, etc...?) At this point, I've only seen a little of both languages, so I have no real preference. Any input, especially if you're using one or both in the field, would be very helpful. Thanks, and may all of your K-maps be glitch-free."

Comments

Where are you located?

[hpa]

Personally, I would say that Verilog is more C-like: weakly typed, compact, efficient notation, whereas VHDL is much more Ada-like: strongly typed, often verbose, but can catch errors that the other one can't.

In industry, as far as I can tell, Verilog seems to be more used in North America and VHDL in Europe, so that might affect what you care about, too.

Personally, I prefer Verilog.

Re:Where are you located?

[phulshof]

I agree with the above post, though I personally prefer VHDL. That might however have something to do with me having designed ASIC/FPGAs for about 11 years now using VHDL though. :) Both are very powerful languages these days, and I see no problem in teaching a course using both languages, showing how to create the same hardware using different language constructs.

Re:Where are you located?

[Man On Pink Corner]

Speaking as someone who just got his first Verilog-based design working on a Nexys2 board, I can confidently say that there are two serious mistakes a n00b can make:

1) Thinking of Verilog (or any HDL) as anything like C. Yes, there are semicolons. Yes, you can write a "for" loop, if you want to synthesize a huge mess. That's about it.

2) Thinking of Verilog as a programming language at all. HDL stands for "Hardware description language," and that's what they are.

Verilog is fun stuff, but it's the hardest thing I've ever taught myself. For those who are trying, I've found the Bhasker books on synthesis to be quite useful, Pong Chu's FPGA Prototyping with Verilog Examples to be reasonably useful, and most of the others to be fairly worthless. Too many books focus on simulation at the expense of synthesis practices, IMO.

Also have just received Richard Haskell's new books on basic and advanced Verilog using the Basys and Nexys2 platforms. They look very good at first glance but I haven't yet had a lot of time to spend with either of them.

Re:Where are you located?

[SydShamino]

Having now read through the entirety of the comments on this story, the trend I see is that:
A) students who learned with VHDL then went on to a career with Verilog think the transition was easy and either language is fine, while
B) students who learned with Verilog then went on to a career with VHDL, while rarer, think VHDL is a harder language, and
C) students who were forced to take VHDL when it wasn't in their career plan hated it, because it was so different than a programming language.

Based on that review, I'd say teach your students VHDL. The students that learn it and do well in your course will have the easiest time in the industry, and those that hate it probably won't become good HDL designers regardless.

VHDL of course

[wiredlogic]

Let's put it this way. I once implemented a subset of TCL in pure VHDL to implement feature rich scripting for simulation data. That can't be done in Verilog without dropping out to C.

VHDL == history

[whoever57]

There were very good reasons why people used VHDL in the past. Because VHDL was an open language before Verilog, the cost of VHDL tools was historically lower than Verilog tools. Since this cost was much more important to FPGA designers, VHDL tended to dominate the FPGA market.

On ASIC side, the first mainstream commercial synthesis tool was Synopsys and Synopsys chose to support Verilog before supporting VHDL. Amongst all the other NRE costs in designing an ASIC, the added cost of using Verilog tools (instead of VHDL) was not really significant. Also, tools to support large designs advanced initially as Verilog tools.

Fast forward few years and Verilog is now open, the cost differential has now disappeared. However, VHDL had a lot of features related to design validation that were not in Verilog. In VHDL you can read and write files. Such things as configurations are supported, etc.. This type of capability makes it easier to write a testbench in VHDL, while on the Verilog side, additional tools and languages are commonly used.

Fast forwards a few more years to today and now we have System Verilog. This gives Verilog the capabilities that it lacked in comparison to VHDL and probably more. The price of VHDL tools is the same as Verilog tools.

Summary: it's clear that the future does not belong to VHDL. It looks like System Verilog is the future, although there are other contenders. So, if the choice is between VHDL and Verilog -- pick Verilog.

Re:VHDL == history

[gwait]

When I got into verilog, there was no standard method to support Silicon Asic libraries in VHDL, so verilog owned the Asic market.

I've done both, currenly VHDL, but found Verilog easier to use, both for design description and for testbenches. Verilog (or at least Cadence-XL) has always had file read/write access, and a linking setup very reminiscent of the way a C compiler works, that and the fact that it offers an "include" mechanism like C makes it very easy to compile and link in various test "programs" into the whole testbench.
I found it very surprising how difficult this is to do in VHDL actually.
Some designers I know glue TCL scripts in to handle testbench functions instead of doing so natively in VHDL..

Re:VHDL == history

[stevew]

I've been in the industry as a chip designer since 1995 (board designer for 15 years before that..) I learned Verilog in about 2 days because I knew C thoroughly. My experience applies to someone who is already a designer - which isn't the case here.

I also know that there are some limitations of the original definition of VHDL that make it a pain to use. The strong typing gets in the way of getting the logic described. VHDL natively can't do things like signed arithmetic. That's why you have all those IEEE packages! In other words - the language is extensible - but you pay a price in lack of brevity to describe the hardware you're after.

There are features of 1995 Verilog that also are a curse and a god-send. The assumption that any undefined term is automatically a wire can save you lots of trouble in the creation of the design or bite you in the posterior (where a strongly typed language would save you from yourself.) So Verilog takes on the original K&R attitude of the programmer being smarter than the compiler and knowing what he/she is doing.

No come into the current century and we have System Verilog. System Verilog = Verilog + Vera + the best parts of VHDL (things like generate).

Where VHDL and Verilog were lacking for strong verification methodologies (that in truth were developed years after either language came into being...) System Verilog has been updated to handle this job adequately along with the task of describing the hardware.

The real answer is that you have asked one of those religious war questions - just like VI vs Emacs (Obviously VI is better ;-) Let me give you a URL that you can read about a contest that was held at DAC some years ago - http://www.angelfire.com/in/rajesh52/contest.html

I worked for both Yatin and Larry (two of the conspirators in this story) You be the judge of the Verilog/VHDL war.

I also believe there is a very definite geocentric component to these arguments as has been claimed in earlier posts - In the US Verilog is dominant - while in Europe it's VHDL. I can't speak to other continents. ;-)

In my time as a consultant in the field - I've had two projects out of roughly 20 that were VHDL. Now-a-days these tend to be multi-language affairs where we have both VHDL and Verilog mixed together. Modelsim, and the Cadence offerings handle this pretty transparently (can't speak to the Synopsys tools - haven't used them in better than a decade at this point.)

As another data point - the vast majority of reusable IP that I've seen was done in Verilog. (This may be due to the geographic component - mostly US companies.. ARM being the exception - but everything I see from them is primarily in Verilog... ;-)

Okay - that's lots of data as to what you should do - I would think you should concentrate on teaching about the synthesis subset, proper digital design AND how to write verification environments before they ever even WORRY about FPGAs. What I've seen are a lot of non-designers getting into FPGA design - and they are clueless about things like clock domain crossing and testing the design in simulation BEFORE they go to the FPGA. The old 90/10 rule applies equally here. Do the homework on the design FIRST with simulation before you try to debug every little problem when it's been realized in hardware as an FPGA. I would imagine that students who are trying to become designers are going to suffer the same pitfalls if not shown the RIGHT way to do things.

Hope this gives you some data. In the long run - whether you use Verilog, VHDL or better yet - System Verilog doesn't matter so much as teaching the proper design and verification methodologies!

Re:System Verilog

[PSargent]

I disagree with the statement that everybody has switched to System Verilog. I've worked with a few companies introducing it, and System Verilog is exactly the reason I want to go back to working with VHDL. It's horrible.

My take on it it is that a load of C++ engineers looked at Verilog and thought "What this needs is object orientation!" completely ignoring the fact that hardware description languages are OO by nature. After all, what is a module if not a method of encapsulating design leaving just a public interface.

The result is a horrible mess of a bi-polar language that can't decide if it's a software language or a hardware one, and the two sides don't really want to talk to each other. Add to that the fact that all of the design patterns that are being used with it are software patterns that don't map well to hardware, that most hardware engineers don't know, and you just get a big steaming pile when you try to introduce it to a company.

The EDA vendors love it because it's giving them a new set of tick boxes they can sell their wares on, but I've yet to see it do anything that I couldn't do in straight verilog / VHDL + a little PLI/FLI, and I've been working as a system verilog application engineer for one of the EDA companies. ...oh and it's really slow (as in orders of magnitude).

Advice from a former instructor of VHDL and FPGAs

[StandardCell]

It's been about ten years since my TAs and I taught the lab section of the advanced digital logic design at my university. I agree that, generally speaking, VHDL is a better teaching language than Verilog. Part of the reason is that Verilog, being much like C, is inherently procedural. You don't want to think procedurally with digital logic except for the specific case of state machine design, and even then you have to take into account concurrency. It is this fundamental aspect of concurrency in HDLs that is key to being able to design effectively. I can define twenty clocks going into counters, just like I can wear twenty watches on my arm and have them all tell time independently and/or at different speeds. You can't really do that with procedural languages unless you're talking about thread scheduling, and then this becomes a thread scheduling exercise when you have multiple threads. Even then, you will never be able to get the speed of digital logic because you have instruction fetch, instruction decode, etc. that introduce latency that cannot be reduced even in a multi-core CPU. Not thinking procedurally will help, and the strong typing of VHDL over Verilog will help greatly in my opinion. Those Karnaugh maps you talk about are fine to learn, but HDLs use case statements in VHDL that make state machine design trivial especially when you have >8 states.

Beyond HDLs, however, are FPGAs and ASICs (and I've designed using both). Putting the differences between FPGA and ASIC aside, FPGA has some very specific ties to the vendor because of the way the FPGA is architected. Assignment of I/O, synthesis, and most of all timing constraints for guiding the "map place and route" tools for FPGAs are something you won't learn from VHDL alone (e.g. clock domain frequencies, max/min delays, input/output delays, false/multicycle paths, setup and hold times or worst-case timing paths in the design). These are essential to digital design, but not part of the HDL at all (see Synopsys SDC format for more info). In fact, shell scripts, sed/awk, Perl, TCL, Scheme and Python are also essential to know because they glue the various different tools together through scripting, processing of text files, tailing log files, and batching can be critical to being efficient. So is being thorough in understanding log file warnings and errors, timing reports. Electronic Design Automation or EDA tools also have their own idiosyncrasies, and you'll need to develop a stable "reference front-end and back-end design flow" if you haven't already. Do you use an Altera or Xilinx reference board, or an add-on PCI-based FPGA card? And how do you analyze what's coming and going at the interface? All of these questions need to be answered before you really get going on FPGAs. ASICs have an order of magnitude more complications for reasons I won't even discuss, but it just gets harder. So those state machines that you created without K maps will have synthesis pragmas that direct the compiler to create the appropriate state machine (e.g. One-hot for performance, Gray code for lower power, etc.).

Finally, there's the work world. As other posters have mentioned, North America is primarily focused on Verilog while the rest of the world is VHDL. Most synthesizable IP cores for various functions come as Verilog. So, the truth is, you should know both major HDLs, but you would be better off being proficient in Verilog in the real world for the simple reason that it is the present and future (or at least its successors, such as System Verilog, are the future) are for many reasons. Also, in the work world, it's critical to know the major EDA vendor software and to put it on your resume (i.e. Mentor Graphics, Synplicity (for FPGA), Synopsys, in roughly that order, and Cadence and Magma for ASIC) as well as all those scripting and other languages like Perl and TCL that I mentioned. Don't completely ignore VHDL, however.

As an ironic point, there are SystemC compilers for hardware that are becoming more and m