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ARM Launches Cortex-A5 Processor, To Take On Atom
bigwophh writes "ARM launched its new Cortex-A5 processor (codenamed Sparrow) this week, and while it's not targeted at the top end of the mobile market, it is a significant launch nonetheless. The Cortex-A5, which will likely battle future iterations of Intel's Atom for market share, is an important step forward for ARM for several reasons. First, it's significantly more efficient to build than the company's older ARM1176JZ(F)-S, while simultaneously outperforming the ARM926EJ-S. The Cortex-A5, however, is more than just a faster ARM processor. Architecturally, it's identical to the more advanced Cortex-A9, and it supports the same features as that part as well. This flexibility is designed to give product developers and manufacturers access to a fully backwards-compatible processor with better thermal and performance characteristics than the previous generation."
The Cortex-A5 is aimed at phones. The Cortext-A9 is the one aimed at netbooks. The article referenced in the summary makes this clear.
http://arstechnica.com/gadgets/news/2009/10/arm-fills-out-cpu-lineup-with-cortex-a5.ars
http://www.brightsideofnews.com/news/2009/10/21/arm-announces-cortex-a5-for-the-next-15-billion-cellphones-and-mids.aspx
If it's not superscalar, why does it need a branch predictor? It only needs to know when the first instruction fails a cache hit, so that any results can be held.
Uh, what? You need a branch predictor because it's pipelined. It has an 8-stage pipeline, which means that it doesn't know the result of an instruction until eight cycles after it was issued. If you come to a conditional branch, you need to decide whether to take it or not. For example, if you have some C code saying something like 'if (a == 12)' then you can't decide whether to jump to the else block until you've computed the value of a, which will be 8 cycles in the future. Without a branch predictor, you just stall for 8 cycles and do nothing. Given that compiled code averages about one branch every 7 instructions, that means that you would be spending most of your time doing nothing.
The branch predictor makes a guess about which branch to follow, i.e. whether to continue to the body of the if statement or jump to the else block. It then starts executing whichever branch if guesses. If it guesses correctly, then the pipeline stays full. If it guesses incorrectly, the pipeline is flushed and none of the results of the instructions after the branch missprediction are committed. The processor resets itself to the branch and continues down the right track.
The branch predictor in the A5 gets about a 95% hit rate, so on average you have to flush the pipeline every 20 branches, which isn't too bad in terms of overhead. Superscalar makes no difference to the need for branch predictors. A superscalar chip is one that can issue more than one instruction per cycle. That means that independent instructions can be run side by side. This is quite nice on ARM chips, where a lot of instructions are predicated, as you can run both versions in parallel and only commit the one that was meant to be taken, but it's completely independent of the branch predictor.
It doesn't sound like it is necessarily slower, either, since you can get the same functions as the A8.
Nonsense. By that logic Atom is as fast as a Core 2 because you have the same instruction set on both. The A5 and A8/9, due to massive implementation differences, will execute different numbers of instructions per clock and not run at the same clock speed. The A5 will execute far fewer and runs at a lower frequency.
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And it's full of misinformation:
1) The A5 is not meant to take on Atom. The A9 is.
2) The A5 is not architecturally identical to the A9. The A9 is an in-order, multi-issue core. The A5 is an out-of-order, single-issue core. The only thing similar is it has the Cortex A-series ISA.
What the A5 is is a CPU that completely obliterates the ARM11-derived cores, used in everything from NVIDIA Tegra to the Nintendo DS. It's an update of the ISA, and a more capable core, with better thermals. That's it. Whereas every low-end smartphone now has the same damn QualComm ARM11-based core, in a year, they'll all have the A5.
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