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Intel-Micron Joint Venture Develops 25nm NAND
Ninjakicks writes "IM Flash Technologies is a joint venture between Intel and Micron that is targeted for producing NAND flash memory. With a focus on R&D, IMFT has doubled NAND density approximately every 18 months. Tomorrow IMFT will announce the launch of their 25 nanometer NAND technology — a major advancement in the semiconductor industry. Intel and Micron can now lay claim to the smallest production ready-semiconductor process technology in the world. IMFT took members of the press on a tour of the new 25nm fab and it's an interesting view into this bleeding-edge manufacturing process."
Those JMicron drives were absolutely horrible - 4KiB of SRAM cache, later doubled to 8KiB? Even Intel's lowest end SSDs have 256KiB, plus another 32MiB of RAM for caching the locations of free spots to write files.
Oh, btw - the cache has to be SRAM so that if the power goes out, it can write the files when it comes back on. SSDs absolutely must have a RAM cache so that they can efficiently locate places to write files, or they will stall while the controller tries to locate one. That's why the low end controllers perform so horribly in random write.
But now even the worst controllers aren't too bad. If I remember right JMicron's newest low-end controller has 128KiB of cache, and there are cheap Intel knockoff SSDs coming out that perform decently. (same controller, but less RAM cache and less space) If what you want is blazing fast loadtimes in games, they aren't bad options, but they're still slower than a fast HDD and have way less space.
in the olden days, xx nm really meant feature size. With Intel and other fabs pressing mfg to half the size every 2 years, it seems mfg has gotten quite creative in their definition of feature size. Latest feature size is a fraction of the wavelength of the light used for patterning, and to achieve it, double and sometimes triple patterning is used. That is basically multiple exposures with slight offsets. The result migh be called 25nm but might really be 50nm, and edge sharpness when you are at 1/4lambda is so suspect that you really have to add some margins here and there, and some features dont really lend themselves to double and triple patterning, so you really have a mix including 50nm process for these.
Kind of like a marketing gimmic, just here it is engineering selling it as 25nm to their own marketing departmens.
don't cut it off www.mgmbill.org