Intel Details Upcoming Gulftown Six-Core Processor
MojoKid writes "With the International Solid-State Circuits Conference less than a week away, Intel has released additional details on its upcoming hexa-core desktop CPU, next gen mobile, and dual-core Westmere processors. Much of the dual-core data was revealed last month when Intel unveiled their Clarkdale architecture. However, when Intel set its internal goals for what its calling Westmere 6C, the company aimed to boost both core and cache count by 50 percent without increasing the processor's thermal envelope. Westmere 6C (codename Gulftown) is a native six-core chip. Intel has crammed 1.17 billion transistors into a die that's approximately 240mm sq. The new chip carries 12MB up L3 (up from Nehalem's 8MB) and a TDP of 130W at 3.33GHz. In addition, Intel has built in AES encryption instruction decode support as well as a number of improvements to Gulftown's power consumption, especially in idle sleep states."
Can most programmes really be written to take advantage of so many cores? I am not sure I want to have a 6-core processor, of which 5 spend most of the time idling as I am only running a single-core-aware programme. OK, one more core can be used by the OS to make everything snappy, but the question stands.
Perhaps a jump in number of cores will convince people outside the Apple and FreeBSD camps to port Grand Central Dispatch.
Letting the kernel team handle the hairier parts of multi-threaded design should make it easy for barely-optimized software to use powerful hardware.
Could its Apache license work with the #1 OS family?
I'll be your candy shop of infinite deliciousity if you'll be my discotheque of endless rump-shaking.
So I skimmed TFA (gasp!) and it appears that Intel is finally following AMDs lead by keeping thermal envelopes constant.
I note that this is still a effectively 2 CPUs with 3 cores each, but that's better than legacy Intel approaches, which would have been 3 sets of dual cores.
It will be interesting to see how independent performance benchmarks play out between the new processors that are coming out.
The cesspool just got a check and balance.
Instead of churning out cores they schould tweak the x86 isa to use multiple cores efficently. 1/2-word Atomic compare and swap is not enough, you cannot make atomic lockless doubly linked lists with that. No wonder something as interesting as http://valerieaurora.org/synthesis/SynthesisOS/ is not possible on x86 without major hacks.
And yet, latest ARM cores are much closer to that 68k transistors from 1980, while not being nearly that far behind i7 in performance as the relation between numbers of transistors would suggest.
Perhaps ARM found the sweet spot.
One that hath name thou can not otter
24 x86 cores just doesn't compare to 1 Fermi with 512 striped down vector processors