Slashdot Mirror
Junctionless Transistor Could Simplify Chip Making
An anonymous reader writes "A novel transistor architecture has been developed by a team of researchers led by Jean-Pierre Colinge at Tyndall National Institute at Cork, Ireland. Not many technology developments can be truly described as 'a breakthrough' or "revolutionary' but this might just fit the bill. It does depend on the extremely small dimensions of silicon nanowires just a few dozens of atoms wide. EE Times picked up on an announcement of a paper on the topic being published by Nature Nanotechnology."
The gate can be used TO squeeze the electron channel to nothing without the use of junctions or doping.
Yes, they mean "please fund my research".
I didn't see anything that suggested fabrication would be easy.
I saw the headline but thats about all I read.
Yep, the A8 gets 2 DMIPs/Mhz vs the P3 at ~1.1 DMIPS/Mhz.
There are 4 boxes to use in the defense of liberty: soap, ballot, jury, ammo. Use in that order. Starting now.
The A8's theoretical maximum is 2 DMIPS/MHz. The P3's theoretical maximum is 3 DMIPS/MHz. In reality, I suspect the P3 is a bit ahead as it is OoO and -- if code is scheduled right -- can actually achieve the equivalent of ~5 ARM instructions (one complex instruction, 2 simple instructions can be decoded each cycle) each cycle.
The ARM is in-order and can decode/issue only 2 ARM ops per cycle. Of course, the A8 uses far fewer transistors than even the earlier P3's without its cache.
The lack of a junction is not unique, ever heard of a MOSFET, "There is no pn junction, so there is no depletion region."
I would assume the article means there's no P-N barrier. MOSFETs don't have a gate-junction but they do have 2 sets of wells. From what I could read in the article, this seems like a single sliver of silicon.
Gate leakage is an issue but the true bane of transistor power consumption is Rdson (resistance drain to source when transistor is on). The reason for the massive heat sinks and fans on processors today is not due to gate leakage its due to the resistance of the transistor channels and the various interconnects.
Yes and no. In modern high-performance ASICs -- that is, the ones that run massive heatsinks -- the leakage current is actually close to matching the dynamic current; worst case dynamic current to boot. In 45nm HP, it actually overtakes dynamic current for realistic chip operation on something like a microprocessor; since most of such a chip is idle even at full load.
Granted the future is mobile silicon and those will invariably use thick-gate processes where leakage is, once again, only a small fraction of switching current but that's at a significant sacrifice to switching frequency.
The thing to keep in mind is that dynamic current only occurs for a fraction of the clock period; leakage is constant. With clock-gating being used on just about every chip out there, it's even less of an issue.
Ever since 65nm, it isn't even "tiny" anymore -- well, relatively speaking. We're talking ~2 uW for an AO22 gate. But again, that's the high-performance processes.