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Microsoft Announces End of the Line For Itanium Support

WrongSizeGlass writes "Ars Technica is reporting that Microsoft has announced on its Windows Server blog the end of its support for Itanium. 'Windows Server 2008 R2, SQL Server 2008 R2, and Visual Studio 2010 will represent the last versions to support Intel's Itanium architecture.' Does this mean the end of Itanium? Will it be missed, or was it destined to be another DEC Alpha waiting for its last sunset?"

31 of 227 comments (clear)

  1. Of course it means the end. by John+Hasler · · Score: 5, Funny

    How could anyone possibly have any use for servers that don't run Windows?

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    1. Re:Of course it means the end. by C0vardeAn0nim0 · · Score: 4, Funny

      yeah, servers with windows are like women playing soccer on high heels. nice to look at, until one of them falls and breaks an ankle.

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    2. Re:Of course it means the end. by the+linux+geek · · Score: 4, Informative

      Exactly. Approximately 85% of Itanium servers are running HP-UX or OpenVMS. Windows and Linux are roughly split on the remaining 15%. Itanium faces challenges, but they're from POWER and SPARC, not from Microosoft killing Windows.

    3. Re:Of course it means the end. by $RANDOMLUSER · · Score: 4, Funny

      or upgrade from Alpha (for VMS shops) or upgrade from MIPS for NonStop shops

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    4. Re:Of course it means the end. by jmauro · · Score: 4, Insightful

      Competent CPU designers, yes. It's the only reason Itanium has lasted this long. Intel's solo early designs were less than successful. HP designer came in redid the whole thing and lo-and-behold it worked. HP really needs Intel to fab the chip, not design it.

  2. Oh Noes! by fuzzyfuzzyfungus · · Score: 4, Insightful

    It would appear that the good ship Itanic has struck an MS Iceberg 2010 Datacenter Edition R2!

    Seriously, though: is this an admission by Microsoft that HP-UX is(somehow) hanging on at the high end, despite HP's every attempt to mismanage it, or (more likely) is this a consequence of the fact that, at this point, there is nothing Itanium can do that Intel couldn't do better and cheaper just by bolting some extra cache and a few extra Itanium features onto Xeons?

  3. The Itanic was Gandalf by overshoot · · Score: 3, Funny

    With Alpha finally gone for good, its job is done and it can now sail off into the West.

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  4. DEC Alpha? by Jeff- · · Score: 4, Insightful

    I am incredibly offended that you would compare this bloated, brute-force, abomination of a chip to the incredibly well designed, elegant, and efficient Alpha (may it rest in peace).

    1. Re:DEC Alpha? by mihalis · · Score: 3, Informative

      ...Both Alpha and Itanium were in-order...

      IIRC the Alpha 21264 was out of order actually, see http://courses.ece.illinois.edu/ece512/Papers/21264.pdf

  5. Doubt it. by Jah-Wren+Ryel · · Score: 5, Interesting

    Does this mean the end of Itanium? Will it be missed, or was it destined to be another DEC Alpha waiting for its last sunset?

    Kinda funny to make that comparison since the Alpha was killed to enable the Itanium. (Long story involving HP making a deal with Intel to hand over the last of PA-RISC/Itanium processor development to Intel and DEC killing Alpha at the same time to clear out the market since HP was in the process of purchasing DEC/Compaq, although the acquisition was not yet public at the time of the cpucide).

    But I doubt its the end of Itanium. Itanium models have things that even the latest Xeons don't in terms of RAS. Most customers don't care about the level of fault tolerance and reliability, but the ones who can't migrate to linux (or Windows) because they are dependent on features of more proprietary OSes like Tandem (now HP) NonStop do need Itanium, and their software is unlikely to be ported to x86 anytime soon (it took at roughly 4 years to get NonStop ported to Itanium to begin with).

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    1. Re:Doubt it. by dave562 · · Score: 4, Informative

      The WSJ mentioned that Intel was porting a lot of the Itanium specific fault tolerance features over to the Xeons.

    2. Re:Doubt it. by stevel · · Score: 4, Interesting

      I thought Intel had partnered with DEC to make the Alpha chip. Also Intel held the patents on it. Intel finally decided to tell DEC sorry but we (Intel) do not want to use these (the Alpha chip designs) anymore. Or something like that anyway. Intel forced DEC to stop making the CPU which left DEC screwed.

      Sorry, that is not even close. DEC sued Intel over infringements of the Alpha patents in Pentium processors. One of the results of the settlement was that Intel acquired DEC's Hudson, MA fab (which still operates today). In no way were DEC and Intel partners in Alpha, though ironically, Intel ended up making Alpha chips in the Hudson fab for several years under contract to DEC. What killed Alpha was years of neglect by Bob Palmer (DEC CEO) followed by Compaq's cluelessness. HP ended up with both Alpha and Itanium and bet the farm on the latter, but by that time it probably didn't matter.

  6. Re:Not Very Comparable by _merlin · · Score: 4, Interesting

    Having used Alpha workstations, I beg to differ. The Alpha was a design that managed to do the absolute minimum per clock cycle in each pipeline stage. This allowed very high clock speeds, and high theoretical peak performance with very deep pipelines. In reality, the deep pipelines' branch misprediction penalty was so bad you never got close to the theoretical peak performance, and the high clock speeds made them hot and unreliable - poor reliability was the main driving factor for switching to SPARC. Everyone should've been able to see the problems with the Pentium 4 well in advance - it was basically an Alpha with an x86 recompiler frontend, so it suffered from all the same problems.

    DEC Tru64 had a lot going for it - lots of good ideas in there. When DEC and HP merged, they should have taken what was worthwhile from HP-UX and integrated it into Tru64, then ported the result to HP-PA. That would've produced a system that people wanted. (HP-UX horrible - nothing behave quite how it should. I'd be surprised if the thing really passed POSIX conformance without some money under the table.)

  7. Every Chip is a DEC Alpha by SwedishChef · · Score: 3, Insightful

    They all get outmoded.

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  8. Re:Not Very Comparable by damn_registrars · · Score: 4, Interesting

    The Alpha was a design that managed to do the absolute minimum per clock cycle in each pipeline stage

    That is pretty much what RISC was about, in a nutshell.

    and the high clock speeds made them hot and unreliable

    I don't know what system you were running. I was using an AlphaServer ES40; four 667 Alphas with 8gb RAM. It was one of the most reliable systems I've ever used for HPC. There was a rack of intel x86 systems of the same era right next to it - something like 32 Intel Xeon CPUs - and the Alpha made the rack look silly and wasteful. On BLAST, the Alpha ran circles around the intel rack, and it became even more embarrasing for the intel rack when the data sets got larger. That was only one example, though; we found pretty much anything we could get source code for, the Alpha ran better. And that was going up against 1.8ghz Xeons.

    By comparison, the Itanium wants to run native 32bit code (though it certainly doesn't do it well). The compilers aren't easy to setup (even in Linux) and it's hard to find a Linux distro that runs on one. I have an SGI cluster with Itanium2 CPUs in it; I know the care and feeding for this system well.

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  9. No one can stop the x86 train, not even Intel. by A12m0v · · Score: 4, Insightful

    No one can stop the x86 train, not even Intel.

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    1. Re:No one can stop the x86 train, not even Intel. by Anonymous Coward · · Score: 5, Funny

      No one can stop the x86 train, not even Intel.

      Maybe not. But certainly some people are trying to strong-ARM the situation.

    2. Re:No one can stop the x86 train, not even Intel. by TheRaven64 · · Score: 4, Informative
      Not yet, no. Unlike x86, the ARM architecture is quite clean. When you go from x86 to x86-64, you get more registers.
      • You go from 8 registers with a load of instructions that require specific registers to be used as operands to 16 general purpose registers. ARM has 33 GPRs already.
      • You get to compile code assuming that it has SSE, rather than the old x87 FPU (which is really hard to generate efficient code for due to its stack-like-but-not-quite design). ARM already has a sane FPU design.
      • You get to guarantee the existence of fast system call instructions. ARM already has fast interrupts.
      • You get an extra addressing mode that makes position-independent code much faster. ARM already has lots of useful addressing modes.
      • You get page-level readable-but-not-executable support. ARM already has this (actually, so do most x86 recent chips).
      • You remove a lot of cruft. ARM already has Thumb and Thumb-2 instruction sets that let you produce very dense code (16-bit instructions) for good instruction cache usage by eliminating the less-frequently-used instructions.

      You also get more address space and bigger registers. Bigger registers are not such an issue with ARM. If you are using 64-bit operands, you have to split them between two registers, but that still leaves you with as many 64-bit GPRs as x86-64 has.

      What about a bigger address space? This is really two issues: the physical and virtual address space. The physical address space is the amount of real memory the processor can access. Current ARM systems ship with 64-256MB of RAM. I think there may be a few with 512MB, but they're quite rare. Low power DDR is a lot more expensive than desktop / laptop RAM so these numbers are going to stay lower than laptop and desktop versions. Obviously, people will eventually want handhelds with more than 4GB of RAM, but it probably won't happen for a little while.

      Note, however, that things like PAE on x86 allow you to access more than 4GB of physical address space. All that you need to do is extend the page tables slightly. On post-Pentium x86 chips, the page tables can map from a 32-bit virtual address space to a 36-bit physical one. This means that you can access 64GB of physical memory, but individual processes are limited to 4GB (unless they do some ugly things). This kind of thing is much easier for ARM because, unlike x86, the ARM architecture does not guarantee backwards compatibility in the privileged instruction set. They could quite easily extend the physical address space without changing the unprivileged instruction set, so you'd need to modify the kernel but no userspace stuff. I won't say 64GB ought to be enough for anyone, but a handheld with more than 64GB won't be affordable for many people for several years.

      That leaves the virtual address space. I'm currently running a 64-bit OS on a 64-bit CPU and looking at my running processes, the biggest one is using around 750MB of virtual address space. the largest I've seen on this machine is around 1.2GB. That was a web browser, and there is no real reason why it should be using that much address space: for security, I'd rather that it ran more processes, isolating each site into a separate instance. During my PhD I did a lot of stuff that involved much larger processes, but I don't imagine ray tracing large volume data sets on an ARM machine any time soon.

      That's not to say that there aren't things that benefit from a larger virtual address space. If you're doing video editing, for example, it makes life a lot simpler for the programmer if you can just mmap() the raw data files, which, at around 10GB/hour, can easily consume 100GB of virtual address space for a medium sized project. Of course, you can just stream the data as it's required. This involves some extra copying, but it's not a huge amount of effort, and most existing code does this anyway.

      If your process doesn't need more than 4GB of virtual address space, then there's a significant

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  10. Re:Not Very Comparable by Bert64 · · Score: 4, Interesting

    The alpha didn't even attempt to do out of order execution until the EV6 chip...
    The EV4 and EV5 chips were strict in-order processors.

    The difference with the P4, is that the p4 was expected to run code that was originally optimized for a 386, whereas the original alpha had code that specifically targeted it... In-order execution works very well when you can specifically target a particular processor (see games consoles), since you can tune the code to the available resources of the processor... The compiler for the alpha was also pretty good, it could beat gcc hands down at floating point code for instance.

    In terms of alphas getting hot, the only workstation i remember which had heat problems was the rather poorly designed multia (which used a cut down alpha chip anyway).. other alpha systems i used were rock solid reliable and i still have several in the loft somewhere - one of which ran for 6 months after the fans failed before i noticed and shut it down...

    Clock for clock the alpha was pretty quick too, unlike the p4 that was considerably slower than a p3 at the same clock...
    http://forum.pcvsconsole.com/viewthread.php?tid=11606 shows alphas getting specfp2000 scores higher than x86 chips running at 3x the clock rate.

    A lot of people, myself included, think itanium should never have existed, and that the development effort should have been put into alpha instead - an architecture that already had a good software and user base...

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  11. Re:Sans Red Hat too by Luke+has+no+name · · Score: 3, Funny

    Debian 27 plans to drop support.

  12. Re:Probably not by lgw · · Score: 5, Interesting

    Microsoft has had a strict policy since the dawn of Windows that Windows be built for at least 2 processor architectures at all times. They really worried about i386-isms creeping into the kernel. It pretty much doesn't matter what 2 you choose, as long as it's more than one (and they're somewhat different), it keeps the kernel devs honest. I wonder what they're doing now: perhaps they just decided that i386 and "amd64" are different enough to serve their purpose.

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  13. Re:Probably not by bhtooefr · · Score: 3, Interesting

    The other thing is, keep a full build internally.

    The rumor mill says that Microsoft has current versions of Windows built for ARM internally... sorta like how Apple kept x86 builds of Mac OS X internally the whole time.

  14. Re:Not Very Comparable by epine · · Score: 4, Interesting

    If the 1.8GHz Xeon was based on the Netburst architecture, first you have to multiply by 2/3rds to correct for diet Pepsi clock cycles, then if your code base is scientific, you have to divide by two for the known x86 floating point catastrophe, and finally, if your scientific application is especially large register set friendly, there's another factor of 0.75. So on that particular code base, a 1.8GHz Netbust is about equal to a 400MHz Alpha (I only ever worked with the in-order edition). Netburst usually had some stinking fast benchmarks to show for itself if it happened to have exactly the right SSE instructions for the task at hand. And it gained a lot of relative performance on pure integer code. BTW, were you running Xeon in 64-bit mode? That could be another factor of 0.75.

    A lot of people, myself included, think itanium should never have existed, and that the development effort should have been put into alpha instead - an architecture that already had a good software and user base

    Yeah, you and a lot of clear headed people with insight into the visible half of the problem space. Not good enough.

    Alpha was a nice little miracle, but it fundamentally cheated in its fabrication tactics. This is a long time ago, but as I recall, in order to get single-cycle 64-bit carry propagation, they added extra metal layers for look-ahead carry generation. For a chip intended Intel scale mass production, this kind of thing probably makes an Intel engineer's eyebrows pop off. That chip was tuned like a Ferrari. I'm sure the Alpha was designed to scale, but almost certainly not at a cost of production that generates the fat margins Intel is accustomed to.

    Around the time Itanium was first announced, I spent a week poking into transport triggered architectures. There was some kind of TTA tool download, from HP I think, and I poked my nose into a lot of the rationale and sundry documentation.

    TTA actually contains a lot of valid insight into the design problem. The problem is that Intel muffed the translation, through a combination of monopolistic sugar cravings, management hubris, and cart before the horse engineering objectives. I'm sure many of the Intel engineers would like to take a Mulligan on some of the original design decisions. There might have been a decent in there somewhere trying to get out. Itanium was never that chip.

    I pretty much threw in the towel on Itanium becoming the next standard platform for scientific computing when I discovered that the instruction bundles contained three *independent* instructions. They went the wrong way right there. They could have defined the bundles to contain up to seven highly dependent instructions, something like complex number multiplication: four operands, seven operations, two results. It should have been possible to encode that in a single bundle. Either the whole bundle retires, or not at all.

    Dependencies *internal* to a bundle are easy to make explicit with a clever instruction encoding format. You wouldn't need a lot of circuitry to track these local dependencies. What you gain is that you only have to perform four reads from the register file and two writes to the register file to complete up to, in this example, seven ALU operations. Ports on the register file is one of the primary bottlenecks in TTA theory.

    What you lose is that these bundles have a very long flight time before final retirement. Using P6 latencies, it's about ten clock cycles for the complex multiplication mul/add tree in this example (not assuming a fused mul-add). This means you have to keep a lot of the complexity of the P6 on the ROB side (retirement order buffer). But that also functions as a shock absorber for non-determinism, and takes a huge burden off the shoulders of the compiler writers. This was apparent to me long before the dust settled on the failure of the Itanium compiler initiative.

    In my intuitively preferred approach, instructions within bundles would be tightly bound and s

  15. Re:Still supported on real OSes like Linux and HPU by Macka · · Score: 4, Informative

    Oh come on. It's really disingenuous to be quoting that kind of shit. Have you ever taken a really close look at the kind of hardware the vendors use to get these benchmark numbers? Database app benchmarks are almost always very sensitive to I/O, and these kinds of numbers are usually generated by systems that have their I/O card slots max'd out, with several hundred (if not thousands) of small high speed disks behind them. The cost of these solutions in real life would be crippling. Vendor quoted benchmarks should usually be taken with a generous pinch of salt.

  16. ding - worse is better by epine · · Score: 5, Interesting

    This is a response to my own post. Sometimes after uncorking a minor screed, I note to myself "that was more obnoxious than normal" and then my subconscious goes "ding!" and I get what's grinding me.

    The secret of x86 longevity is to have been so coyote-ugly that it turns into pablum the brain of any x86-hater who tries to make a chip to rid the planet of the scourge once and for all.

    For three decades right-thinking chip designers have *wanted* x86 to prove as bad in reality as ugliness ought to dictate.

    Instead of having a balanced perspective on beauty, the x86-haters succumb to the rule of thumb that the less like x86, the better. And almost always, that lead to a mistake, because x86 was never in fact rotten to the gore. You need a big design team, and it bleeds heat, but all other respects, it proved salvageable over and over and over again.

    On the empirical evidence, high standards of beauty in CPU design are overrated. Instead, we should have been employing high standards of pragmatic compromise.

    If any design team had aimed merely for "a hell of lot less ugly", instead of becoming mired in some beauty-driven conceptual over-reaction, maybe x86 might have died already.

    Maybe instruction sets aren't meant to be beautiful. Of course, viewed that way, this is an age-old debate.

    The Rise of ``Worse is Better''

    Empirically, x86 won.

    The lingering question is this: is less worse less better, or was there a way out, and all the beauty mongers failed to find it?

    1. Re:ding - worse is better by evilviper · · Score: 4, Interesting

      x86 isn't a passable architecture at all. What it has going for it, is MONEY. Intel, AMD, and others have dumped tons of money into it to keep it moving along, against all odds. This because the whole world is tied to, and fixated on x86, which itself came about way back when, because IBM wanted a second supplier, so x86 was the only chip out there with competition, and therefore no proprietary lock-in. Other companies like DEC, MIPS, ARM, etc., have patents on their tech, with no license agreements, so no real attempt to one-up them. x86 competition out the gate made it a healthy ecosystem, which then precluded all others, which then became self-sustaining.

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    2. Re:ding - worse is better by Panaflex · · Score: 3, Insightful

      Because they figured out that the instruction set means diddle squat in the end - it's the branch prediction, floating point, pipelining and good cache design that makes a difference. Get that right and strap an X86 decoder on the front end and it's perfect.

      We love CPU's that perform, and only a very few people really care what that looks like under the hood.

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    3. Re:ding - worse is better by RzUpAnmsCwrds · · Score: 4, Insightful

      x86 isn't a passable architecture at all. What it has going for it, is MONEY. Intel, AMD, and others have dumped tons of money into it to keep it moving along, against all odds.

      It's fundamentally irrelevant whether anyone thinks that x86 is "passable" - it's a proven fact. We have 15 years of out-of-order x86 implementations that prove that.

      Yeah, you have to handle the brain-dead instruction encodings in the decoder, and you need to emit micro-ops for a bunch of obscure instructions that no one ever uses (to maintain compatibility). You also have to handle the multiple obscure and obsolete memory addressing modes.

      But the reality is that no one but engineers gives a crap about this. In a world of 300M+ transistor cores, there just isn't that much overhead to making the CPU compatible. Most of the die space is cache anyway nowadays.

      We can't compare what x86 is to what POWER or MIPS or SPARC "would have been" in some speculative world where Intel wasn't the dominant desktop/server CPU manufacturer. There's no magic bullet that can make load-store architectures amazingly fast but that doesn't apply to x86. Almost all of the technology out there can apply equally to a modern x86 CPU.

      What sells CPUs is not having a clean and simple ISA. What sells CPUs is performance, power consumption, and, in many cases, compatibility. If having a clean ISA accomplishes those objectives, so much the better. But Intel and AMD have shown that you can make a fast, low-power, compatible x86 CPU and sell it at a very low price. That's what matters.

  17. Re:Not Very Comparable by IntlHarvester · · Score: 4, Interesting

    The Alpha was supposed to run Unix - Tru64 Unix in particular. Running in a proper 64bit environment the Alpha was an incredible chip.

    This is a pretty gross oversimplification. First of all, Microsoft spent a lot of money writing a portable OS partially because the conventional wisdom at the time was that RISC would bury x86. (Keep in mind they could have just kept using OS/2.) Digital also badly needed volume for their chip production and make a somewhat serious attempt at the Windows workstation/server market. That Alpha was pigeonholed as a Unix chip is one of the main reasons it failed.

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  18. Re:Probably not by cbhacking · · Score: 3, Informative

    Just to keep this clear: you're talking about NT (which wasn't even called "Windows NT" initially, internally). NT is almost entirely written in C, and the few architecture-specific parts are abstracted from the core codebase and typically present in assembly modules which are maintained for multiple architectures and which the compiler automatically uses the appropriate one for the current build. There's some use of inline assembly or specifics of x86, but it's all behind #if blocks, with the equivalent checks for other CPU architectures. Overall, NT has been ported to at least 5 architectures that I know of - x86 (32-bit), x64, ia64 (Itanium), PPC, and DEC Alpha. If MS wanted to, it would be possible to port it to ARM, MIPS, SPARC, or almost any other reasonably modern architecture of at least 32 bits.

    By comparison, Win9x has a ton of assembly code that enabled it to run fast even on low-end machines, keeping the system requirements down (and making it attractive to home users back in the days before consumer hardware caught up with the demands of NT). Of course, use of assembly like this has downsides - 9x was badly unstable, and completely non-portable. It only ever ran on x86, and I'm not even sure it made much use of the features found in any version after the i386.

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  19. Re:Not Very Comparable by cbhacking · · Score: 5, Informative

    The POSIX NT subsystem (and Interix, the user-space software that runs in the subsystem) have existed for a very long time, possibly all the way back to pre NT 4. The NT kernel doesn't actually use Win32 (or Win16, DOS, or Win64) system calls; it uses NT system calls,w hich are a superset of the functionality in all of those, plus the functionality required for OS/2 and POSIX. For example, the NTCreateFile system call not only implements the Win32 CreateFile system call (as seen in Win9x) but also the OpenFile system call (Win16) and the open system call (POSIX). For each API that NT supports, there is a user-mode DLL that translates the API-specific system calls (such as open(2)) to NT system calls (such as NTCreateFile()). These are then passed to ntdll.dll, which executes the actual system call (invoking ring-0 kernel code).

    The OS/2 subsystem was discontinued years ago, but the POSIX one is still supported. From XP forward, it's been possible to enable the POSIX subsystem and download pre-compiled libraries, shells, utilities, headers, build toolchain (optionally using GCC or MSVC), manpages, and so forth to produce a working, if somewhat bare-bones, UNIX-like environment. Initially called OpenNT and now known as Interix, various third parties have provided additional functionality such as package managers (apt, portage, pkgsrc, or one specifically for Interix from http://suacommunity.com/ ), additional shells, libraries, utilities, X servers, and more.

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