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Can Transistors Be Made To Work When They're Off?
An anonymous reader writes "Engineers at the Belgian research institute IMEC are looking at the use of silicon transistors in the sub-threshold region of their operation as a way of pursuing ultra-low power goals. A chip the engineers are designing for biomedical applications could have blocks designed to operate at 0.2 or 0.3 volts, researchers said, according to EE Times. The threshold voltage is the point at which the transistor nominally switches off. Operating a transistor when it is 'off' would make use of the leakage conduction that is normally seen as wasted energy, according to the article."
The energy put into thinking about this would far outweigh any perceived benefits.
Indeed. All scientific research is utterly useless and wasted time unless it has immediate and forseeable tangible benefits.
Another commenter is correct in pointing out that what they're doing is using leakage current. When we measure power dissipation, we count two things, (a) dynamic power, which is used when a transistor switches and is a function of frequency, voltage, and temperature, and (b) static (leakage) power, which is always going on and is a function of voltage and temperature. At 180nm, the ratio of dynamic to static was about 1000:1. It started to become noticed at around 90nm and a problem at 65nm. Now at 45nm and 32nm, leakage is about half the total power usage. The best way to lower power is to reduce voltage, but this kills performance scaling. Scaling down transistors reduces dynamic power but increases relative static power, which is why processors like the Core i7 use not just clock gating but POWER gating, dynamically, at a functional unit level.
Regarding subthreshold, as you lower voltage, power goes down. The problem is that transistors also get slower. Above threshold, the power goes down faster than speed, so if you're using a transistor with threshold voltage of 150mV with a supply voltage of 300mV, you get like a 100th the power dissipation, but a tenth the speed, which means that you use one tenth the energy to perform some process. As you lower the supply voltage below threshold, the transistors get slower faster than the power goes down, so total energy actually goes up as you lower voltage below a certain point. There is a supply voltage point either side of the threshold voltage where energy is minimum for the range. You use near threshold or sub threshold depending on if you care about speed. Also, things behave quite differently at low voltages, so you have to change all your design techniques.
One of the problems with near and sub threshold is that you don't actually know what your threshold voltages are anymore. It's called process variation. The transistors are so tiny that you get on the order of tens of dopant atoms per transistor. The doping process is highly random, so you get wide variance on threshold voltage (and effective channel length too), meaning that two transistors next to each other have different switching characteristics. This is actually a major problem at 32nm, resulting in unfortunately large supply voltage margins to avoid timing-related errors, which translates into excessive power usage. It's an even bigger problem when the supply is near the threshold (above or below), because the speed of a transistor and its power output are actually functions of the difference between supply voltage and threshold voltage. If the supply is 300mV, then the transistor with Vth=130 is going to be way faster (and way leakier) than the transistor on the same die with Vth=170. Of course, both were designed to have Vth=150, but you can't control that well enough.
My area of research involves coping with the 5X decrease in reliability at NTC, and I'll talk more about it when my papers are accepted. :)
You're just a fucking ignorant moron.
This has nothing to do with "green" propaganda and raining on your political masturbation parade, and everything to do with looking at ways to overcome the problems that die shrinkage has on causing waste power from static dissipation to prevent further technology advances, you fuck.
The summary is only using "off" in an informal sense. In an idealized textbook transistor model, when the transistor is "off" or in cutoff, it is off completely. But in reality, there is leakage, and so this "cutoff" region actually has some more interesting things going on, then a fucking tool like you apparently would understand. With large transistors in CMOS configurations, there is virtually no leakage and no static dissipation. As features have shrunk, the leakage has become a fully technological advancement problem. It isn't just about treehugging, but also the fact that if you get to a certain point where you have tons of transistors in a small space, if you can't remove the waste heat, you've got a major practical problem.
Get a clue, you useless fucktwit.