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Israeli Startup Claims SSD Breakthrough
Lucas123 writes "Anobit Technologies announced it has come to market with its first solid state drive using a proprietary processor intended to boost reliability in a big way. In addition to the usual hardware-based ECC already present on most non-volatile memory products, the new drive's processor will add an additional layer of error correction, boosting the reliability of consumer-class (multi-level cell) NAND to that of expensive, data center-class (single-level cell) NAND. 'Anobit is the first company to commercialize its signal-processing technology, which uses software in the controller to increase the signal-to-noise ratio, making it possible to continue reading data even as electrical interference increases.' The company claims its processor, which is already being used by other SSD manufacturers, can sustain up to 4TB worth of writes per day for five years, or more than 50,000 program/erase cycles — as contrasted with the 3,000 cycles typically achieved by MLC drives. The company is not revealing pricing yet."
Early adopters will pay for continued R&D, which will then make this affordable for most people down the line. It's how these things work.
With Enterprise SSD's (SLC) still in the $100/GB range, we're far away from general acceptance in the datacenter. MLC also has the problem of being slow to write to vs. SLC which is one of the important metrics when considering SSD's to accelerate your classic spindles. SLC's are reliable enough to last for at least 3 years even fully loaded at 3 or 6 Gbps.
I used some Intel X-25-M and Intel X-25-E's in my environment as they are affordable and generally get the highest scores in IOPS and throughput respectively read and write caches and the performance is way under my expectations. The Intel X-25-E's don't work well under heavy loads on LSI controllers (throws errors and SCSI bus resets) while he Intel X-25-M's do work fine. Every other month there is fresh firmware to fix some or another problem and firmware updating is manual labor with a boot CD, not something you can simply schedule at night or do while the system is online so they are what I would call beta-quality. Especially once fully filled the IOPS performance drops from ~3000 IOPS like a brick to ~1000 IOPS which a small set of hard drives can fulfill so the only good thing it's left for is latency.
We'll see what the Vertex 2 EX brings (Sandforce 1500 controller) which has an advertised 50k IOPS although that might be more marketing than anything. I'm still waiting on a decent priced SAS SSD which can actually sustain 5-10000 IOPS by itself even when fully loaded.
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You have an interesting point there.
Several years ago, maybe back in 2005, Anobit visited us and showed off what they were working on. They were little guys in the flash/solid state business and had come out with this nifty algorithm that would allow the flash with really low read/writes with perform like today's current SSDs.
They were the first (that I know of) to come up with a way to spread the writes across unused portions of memory so that on average, every bit of memory would have the same amount of wear on them. It wasn't until several years later that I saw on Slashdot that Intel had come up with this "new" idea in their SSDs.
Back at the time, the Anobit technology was really cool. But unfortunately, they were prohibitively expensive and we could not use them in our rugged systems.
Seems that they have still been hard at work over there. Very cool. They deserve the success.
Say you're talking about a 4-level MLC cell, and say it runs at 3.3V. If the voltage is on [0V, 0.825V), that's 00b; [0.825, 1.65V) is 01b; [1.65V, 2.475V) is 10b, and [2.475V, 3.3V) is 11b. But those are analog voltages - the controller has to read the voltage, do an analog-to-digital conversion, and figure out which level it corresponds to. The ranges listed above are for if you have perfect discrimination - in most cases, it's difficult to differentiate small differences, so they don't use the full range. With better A-to-D and signal processing, they can resolve the differences better, which in turn lets them get more write cycles.
Those numbers are pulled out of the air for illustrative purposes; I have no idea what the real values are.
This sounds absolutely no different to how all wear-leveled, error correcting flash controllers work. They all use multiple levels of ECC to decrease the error rate. The 'signal processing' they're doing doesn't sound like anything new.
If there is something new going on here, it's absolutely impossible to decode from the layman's language used in the article. All I hear is "Other vendors use X bits for ECC. We use Y bits and we do it in software instead of hardware.", which is basically just another way of saying "Other vendors have 4 blades, we have 5 blades."