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Chips That Flow With Probabilities, Not Bits
holy_calamity writes "Boston company Lyric Semiconductor has taken the wraps off a microchip designed for statistical calculations that eschews digital logic. It's still made from silicon transistors. But they are arranged gates that compute with analogue signals representing probabilities, not binary bits. That makes it easier to implement calculations of probabilities, says the company, which has a chip for correcting errors in flash memory claimed to be 30 times smaller than a digital logic-based equivalent."
This has nothing to do with analog computers. It has to do with probability of error:
ref1: http://www.hindawi.com/journals/vlsi/2010/460312.html
ref2: http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=5118445
No, it does. We aren't trying to reduce error in logic operations. We're passing analog values between one and zero into logic circuits. Literally, at the lowest level, the "bits" pumping through the chip are probabilities. It's not analog in the sense that we use op amps, we still use gates, but the inputs and ouptuts of the gates are probabilities, not hard bits.
It's not the same kind of analog. It's analog in the sense that it operates on things between 1 and 0, but it still uses logic.
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I think it is more of a probability thing then what you are thinking of. The return is the probability that the two values are the same. So 0.5 AND 0.5 would be 100% while 0.5 AND 0.6 would like 80% or something depending on the allowed error and uncertainty.
Thinking of this reminded me of BugBrain. If you want to play with Bayesian logic it has a pretty good set of examples including building a neural network to perform simple character recognition.
It's called fuzzy logic [http://en.wikipedia.org/wiki/Fuzzy_logic].
One way to define it is NAND(x,y) = 1-MIN(x,y)
and the rest follows using usual logic rules.
I have no idea if that's what they do though.
[...] Nowadays Bayesian calculations usually involve thousands of iterations[...]. The simulation then converges to the right answer.
The convergence you refer to is asymptotic. In practice it takes about 10000 iterations to get around a 1% bound on a single probability point estimate, and a factor of a hundred for each order of magnitude improvement. On top of that, if you're dealing with multiple distributions the overall expectation is not just a simple function of the component expectations unless the whole system is linear, you need to use convolution to combine results. And on top of that, lots of interesting problems are based on order statistics, not means/expectations. Having hardware that correctly manipulates distributional behavior in a few CPU cycles would blow the doors off of MCMC.
It's not analog in the sense that we use op amps, we still use gates
What's the difference? A gate is just a high speed high gain ultra high distortion opamp.
Forgot your introductory digital design courses already?
Digital circuits are designed to reliably transmit or compute a digital value in to presence of noise. The way this is done is by excluding huge ranges of voltages and making very high gain op-amps that, while fast, do not need to be accurate. Accuracy is thrown out the window in favor of speed and noise immunity. You will (or should) never see a properly operating op-amp in a digital circuit putting out a voltage other than something in the range representing a 0 or 1 (in TTL-compatible circuits for example, 0 to 0.2 V for a 0 and 4.7 to 5.0V for a 1 ... note that I'm quoting output ranges not input ranges). The acceptable voltage ranges were designed such that a valid 0 signal when combined with inevitable noise would still be read as a 0 at the next stage; mid-range values are not permitted. See, eg, http://www.interfacebus.com/voltage_threshold.html .
Op-amps designed for accurate reproduction of analog values are an entirely different creature, one where accuracy is among the primary design requirements. In contrast to digital circuits, a mid-range value is not only permissible, but expected.
So while both digital and analog logic use op-amps, the design requirements and valid signal ranges are vastly different.
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Based on the reference given above. The idea is to use the possible error rate of a particular assembly of gates to generate a result tha represents a probability. So say, if by lowering the voltage level intentionally and run a particular logic through, the probability of the result is wrong (because of the physical limitations of the device), that would become the desired output, rather than having to raise the voltage to insure the logic is right all the time.
The whole idea is to use less gates and less energy to come up with the same statistical result in a silicon. Organize the gates in different structures will have different probabilities of producing errors. So in theory with enough emperical data we can safely predict the porbabilities of an error coming from a certain arrangements. That is the beauty of the statistics, after all, and it does not have to be dead accurate as long as we are in the margin of errors. The results wills still have the base signals of 0 and 1, except they now represent a certain probabilities, instead of a hard 0 or 1 bit.
Yes the theory is new so it would be hard to validate, but certainly it would be interesting to see how it works out in real-life application.
You mean like a Field Programmable Analog Array?
http://en.wikipedia.org/wiki/Field-programmable_analog_array
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Of course, if they managed to do this using digital IC fab technology (analog ICs are very "big" when you compare to modern digital deep submicron technology), that'll be a huge breakthrough.
That actually wouldn't be a breakthrough at all. I've been designing analog ICs in digital deep submicron technology for 8 years. Some really big companies (Broadcom, Marvel, etc.) have built their businesses on it. I'm currently working on a Pipelined ADC in 65nm CMOS. You may be thinking about Bipolar Analog ICs, which are still important in the marketplace. But, for communications or imaging systems work, the vast majority of analog circuits are on digital CMOS (with or without a special capacitor option).
As an aside, I read recently that they still make close to 100 million 555 timers every year. I wonder what they're used for.
Carl
It's not analog in the sense that we use op amps, we still use gates
What's the difference? A gate is just a high speed high gain ultra high distortion opamp.
Op amps have differential inputs, for one thing. They also generally have much, much higher gain than a gate. Do a voltage transfer characteristic of an inverter in the process of your choice and look at the slope when it is in its linear region. The case won't be any larger than 10 - 15 Volts/Volt. Can't hardly use *that* as an op amp.