Chips That Flow With Probabilities, Not Bits

holy_calamity writes "Boston company Lyric Semiconductor has taken the wraps off a microchip designed for statistical calculations that eschews digital logic. It's still made from silicon transistors. But they are arranged gates that compute with analogue signals representing probabilities, not binary bits. That makes it easier to implement calculations of probabilities, says the company, which has a chip for correcting errors in flash memory claimed to be 30 times smaller than a digital logic-based equivalent."

Comments

Analog Computers

[timgoh0]

It would seem that they have reinvented the analog computer, but this time entirely on a chip. And probably (hopefully) with some logic that prevents errors due to natural processes like capacitive coupling.

Re:Analog Computers

[Anonymous Coward]

No, it does. We aren't trying to reduce error in logic operations. We're passing analog values between one and zero into logic circuits. Literally, at the lowest level, the "bits" pumping through the chip are probabilities. It's not analog in the sense that we use op amps, we still use gates, but the inputs and ouptuts of the gates are probabilities, not hard bits.

There are 10 kinds of people in the world..

[Deus.1.01]

12.5% that understands binary 87.5 that don't...

Re:There are 10 kinds of people in the world..

[jimicus]

Probably.

Re:There are 10 kinds of people in the world..

[Thanshin]

Probably.

User: Are we in the right road to the beach?
Google maps: Probably.
User: the fuck?... Is this the beach road or not.
Google maps: I'd say yes...ish. Most likely. ...
User: The road is cut! It ends like right here!
Google maps: Let me change my first answer to "I wouldn't bet on it. Much. I wouldn't bet much on it. ... Ok no, it's not likely to be the road. I'm turning off now. Good luck!"

Probability in computers: it's called a float

[Z8]

The article mentions Bayesian calculations. Can these computers really speed up those calculations? Nowadays Bayesian calculations usually involve thousands of iterations of a technique called Markov Chain Monte Carlo (MCMC) unless the distributions in question are conjugate priors. The simulation then converges to the right answer.

The issue I see is that all these techniques are just math. They are either analytic (conjugate priors) or require strict error bounds in order get sensible answers (MCMC). There's no separate system of math that Bayesians use. Like many others, Bayesians just need quick reliable floating point mathematics. So anyway, I don't see how this can help Bayesian statisticians, unless it also revolutionizes engineering, physics, etc.

Re:Probability in computers: it's called a float

[Frequency Domain]

[...] Nowadays Bayesian calculations usually involve thousands of iterations[...]. The simulation then converges to the right answer.

The convergence you refer to is asymptotic. In practice it takes about 10000 iterations to get around a 1% bound on a single probability point estimate, and a factor of a hundred for each order of magnitude improvement. On top of that, if you're dealing with multiple distributions the overall expectation is not just a simple function of the component expectations unless the whole system is linear, you need to use convolution to combine results. And on top of that, lots of interesting problems are based on order statistics, not means/expectations. Having hardware that correctly manipulates distributional behavior in a few CPU cycles would blow the doors off of MCMC.

Awesome!

[UID30]

How much longer before we get the "infinite improbability machine"?

Re:may i just say

[dominious]

as a machine learning person

This either means:

You are a person who is learning from a machine or....
You are a learning machine who is now referring to itself as person! You also get excited about probabilities and you are posting on /.

A.I. has gone too far...

Re:1 AND 1 = 1 : 0.8 AND 0.6 = 0.7

[selven]

If 0.8 AND 0.6 = 0.7 (I assume you're taking the average here), then 1 AND 0 would be 0.5, when it's supposed to be 0. The only answers I would accept for 0.8 AND 0.6 are 0.6 (min) and 0.48 (multiplication). An OR gate is constructed by attaching NOT (1 - x here) gates to the inputs and output of an AND gate, yielding 0.8 or 0.92 depending on which rule you go with.

The actual thesis

[Mathiasdm]

By Ben Vigoda, Co-Founder and CEO: http://phm.cba.mit.edu/theses/03.07.vigoda.pdf

Re:The actual thesis

[Born2bwire]

By Ben Vigoda, Co-Founder and CEO: http://phm.cba.mit.edu/theses/03.07.vigoda.pdf

Huh, I thought he was dead.

Re:The actual thesis

[Asic Eng]

Being a chip designer I quite frequently encounter articles which claim that there is going to be a "new way to design chips" coming soon. I'm admittedly a bit jaded hearing about another one.

Often these approaches overstate the problems of current methodologies quite significantly. This thesis too, seems to hit the old favorites. Here is an example: In clocked digital systems, speed and throughput is typically limited by worst case delays associated with the slowest module in the system.

This would be true if clocked digital systems would be restricted to a single clock. Some are, but the embedded devices I work on usually have half a dozen clocks or more. Some modules run with fairly high speeds, others at relatively low speeds - synchronizing them is not only a standard task, it's actually reasonably easy compared with other problems we face.

Very closely related another of their claims: The larger the area over which the same clock is shared, the more costly and difficult it is to distribute the clock signal.

Again - true in principle, but exaggerating the problem. It's not so difficult to distribute a clock over a large area if you allow skew between different areas. That might appear to defeat the purpose, but you really only need to interface reliably between those areas. Skew can even be helpful in some cases: if you send signal X from block A to be clocked-in by block B - then it helps if the clock arrives later at block B than at block A. Of course it's a disadvantage for a signal Y driven from B to A - but that signal might be faster (less logic to go through in block B). Modern design tools can automatically use clock skew to achieve better timing.

One more: Building in redundancy to avoid catastrophic failure is not a cost-effective option when manufacturing circuits on a silicon wafer

Well, we happen to do that regularly, it's cost-effective if you know what you are doing. There are parts of the chip which are much more likely to fail than others - RAMs are more prone to defects than ordinary digital logic. So as part of device testing defective areas of a RAM block can be mapped to a handful of spare cells. doubling every transistor as suggested in the thesis, is not necessary, obviously.

Any of these "fundamentally new" approaches have to compete with the evolutionary solutions which people find for the same problems. That's hard because some of these are at least as clever as the "fundamental" ones, and they are much easier to adapt in existing design flows. I'm not ruling out that at some point we'll switch to a completely different design methodology, just as I'm not excluding the possibility that lighter-than-air travel will at some point find a place in commercial aviation again. I'm just not holding my breath.

Re:1 AND 1 = 1 : 0.8 AND 0.6 = 0.7

[Anonymous Coward]

It's called fuzzy logic [http://en.wikipedia.org/wiki/Fuzzy_logic].

One way to define it is NAND(x,y) = 1-MIN(x,y)
and the rest follows using usual logic rules.

I have no idea if that's what they do though.