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AMD Details Upcoming Bulldozer Architecture
Vigile writes "AMD is taking the lid off quite a bit of information on its upcoming CPU architecture known as Bulldozer that is the first complete redesign over current processors. AMD's lineup has been relatively stagnant while Intel continued to innovate with Nehalem and Sandy Bridge (due late this year) and the Bulldozer refresh is badly needed to keep in step. The integrated north bridge, on-die memory controller and large shared L3 cache remain key components from the Athlon/Phenom generation to Bulldozer but AMD is adding features like dual-thread support per core (but with a unique implementation utilizing separate execution units for each thread), support for 256-bit SIMD operations (for upcoming AVX support) all running on GlobalFoundries 32nm SOI process technology."
It will be drop in compatable with AMD server boards. At home, it will be AM3+.
"AMD's lineup has been relatively stagnant while Intel continued to innovate with Nehalem and Sandy Bridge (due late this year) and the Bulldozer refresh is badly needed to keep in step."
Likely another Intel fanboy trying to spread FUD about the company that he doesn't like and at the same time getting his username posted on the front page.
The facts in that quote were presented clearly. AMD is a generation behind on architecture, trying to get comparable performance by multiplying old cores, while Intel has been advancing architecture and multiplying cores at the same time. For about 4 years now, Intel has had 2-4 chips performing at levels above anything AMD could produce.
It remains to be seen if Bulldozer will put AMD anywhere near at-par on a performance/core basis, but it's not 2002 any more, and AMD has no hope of a performance lead.
Just to be clear, when you say "integer units" you mean "integer schedulers" and not actual integer execution units, of which even the old Athlon's had 3 per core (and that hasnt changed since then.)
Unlike Intel design, with highly asymmetric execution units, AMD's have had 3 symmetric integer execution units per core since the original Athlons. Its actually a pleasant breeze to write hand-optimized integer code on AMD's.
This new design looks (in the diagram) like it actually has 4 symmetric integer execution units per integer scheduler, with the bulldozer having 2 schedulers per core while the bobcat only having 1 per core (I would guess that the logical cores are alternated on rise-and-fall states of the clock on the bobcat, and the diagram certainly makes it look like that is the case.)
Each seem to have two wide floating point execution units, so the floating point performance of both bulldozers and bobcat's are probably equivalent.
What I think AMD has done here is that with the bulldozer, in integer performance it is going to behave like it has 2x the number of real cores. So an 8 core (16 thread) chip will perform much like an 8 core CPU in floatng point work, but much more like a true 16-core CPU in integer work. This should give it a large advantage over Intel in integer work in equal-core comparisons, but the floating point performance will still lag behind Intel.
"His name was James Damore."